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Patent # Description
US-9,378,168 Shared receive queue allocation for network on a chip communication
A circuit arrangement and program product for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting...
US-9,378,167 Enhanced data transfer in multi-CPU systems
A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory...
US-9,378,166 Slave device, master device, communication system, and communication method
In a communication system, a master device gives a data control to one of a plurality of slave devices, and stops controlling data transmission and reception in...
US-9,378,165 Inter-bus communication interface device
There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to...
US-9,378,164 Interrupt return instruction with embedded interrupt service functionality
An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an...
US-9,378,163 Method to accelerate message signaled interrupt processing
Methods to accelerate a message signaled interrupt (MSI) are described herein. An embodiment of the invention includes an interrupt controller to receive a...
US-9,378,162 Handling and routing interrupts to virtual processors
An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical...
US-9,378,161 Full bandwidth packet handling with server systems including offload processors
A rack server system for a packet processing is disclosed. The system can include a plurality of servers mountable in a rack; a top of rack (TOR) unit having...
US-9,378,160 Unified SCSI target management for shutting down and de-configuring a service daemon in a deduplication appliance
Systems and methods are described that manage service daemons using a unified small computer system interface (SCSI) target management daemon. SCSI target...
US-9,378,159 Deadlock detection and recovery in SAS
Systems and methods herein provide for managing devices through a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes a...
US-9,378,158 Universal network interface device
An universal network interface device with an enclosure, an access module, a modem module, a switching power supply and a battery pack.
US-9,378,157 Security memory access method and apparatus
Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory...
US-9,378,156 Information handling system secret protection across multiple memory devices
Information handling system secret protection is enhanced by encrypting secrets into a common file and breaking up the encrypted file into plural portions...
US-9,378,155 Method for processing and verifying remote dynamic data, system using the same, and computer-readable medium
A method for processing and verifying remote dynamic data is provided. The method includes providing a radix tree structure having N levels, obtaining and...
US-9,378,154 Secure reservation mode for logical unit numbers and persistent reservations
A mapping system and method that enables a secure reservation mode for a plurality of logical unit numbers of a storage system, generates a plurality of secret...
US-9,378,153 Early write-back of modified data in a cache memory
A level of cache memory receives modified data from a higher level of cache memory. A set of cache lines with an index associated with the modified data is...
US-9,378,152 Systems and methods for I/O processing using out-of-band hinting to block driver or storage controller
A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a...
US-9,378,151 System and method of hinted cache data removal
The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system...
US-9,378,150 Memory management unit with prefetch ability
Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a...
US-9,378,149 Method and system for tracking modification times of data in a storage system
A method for rebuilding an in-memory data structure. The method includes selecting a table of contents (TOC) entry of a TOC page in persistent storage, where...
US-9,378,148 Adaptive hierarchical cache policy in a microprocessor
A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a...
US-9,378,147 Extended fuse reprogrammability mechanism
An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first...
US-9,378,146 Operand cache design
Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may...
US-9,378,145 Storage controller cache synchronization method and apparatus
A method for a pair of redundant storage controllers to ensure reliable cached write data transfers to storage device logical volumes is provided. The method...
US-9,378,144 Modification of prefetch depth based on high latency event
A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data...
US-9,378,143 Managing transactional and non-transactional store observability
Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The...
US-9,378,142 Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one...
US-9,378,141 Local cache pre-warming
Caching metadata that identify hot blocks at a per local cache level are tracked. Tracked caching metadata are maintained so as to be persistent and shared...
US-9,378,140 Least disruptive cache assignment
The embodiments are directed to methods and appliances for assigning communication network caches. The methods and appliances can assign storage buckets to...
US-9,378,139 System, method, and computer program product for low latency scheduling and launch of memory defined tasks
A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task...
US-9,378,138 Conservative garbage collection and access protection
A method of memory management can include creating an initial root set of pointers for a program during execution of the program and performing a marking...
US-9,378,137 Storage and programming method thereof
A program method of a storage device which includes at least one nonvolatile memory device and a memory controller to control the at least one nonvolatile...
US-9,378,136 Techniques for selecting write endurance classification of flash storage based on read-write mixture of I/O...
Processing I/O operations is described. A write operation writes first data to a first location on a logical device having a logical address space partitioned...
US-9,378,135 Method and system for data storage
A system and method of storing data in a semiconductor-type non-volatile memory is described, where a physical storage address of data is made available to a...
US-9,378,134 Non-volatile memory device capable of minimizing instant current consumption and performing memory operations...
Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a...
US-9,378,133 Autonomous initialization of non-volatile random access memory in a computer system
A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at...
US-9,378,132 System and method for scanning flash memories
A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably...
US-9,378,131 Non-volatile storage addressing using multiple tables
The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this...
US-9,378,130 Data writing method, and memory controller and memory storage apparatus using the same
A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The...
US-9,378,129 Information processing apparatus, control method, and storage medium for memory management and dump processing...
The present information processing apparatus compares a size of a used memory that is currently used for execution of an application with a stored maximum size...
US-9,378,128 Dynamic address translation with fetch protection in an emulated environment
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial...
US-9,378,127 Dynamic memory page policy
Mechanisms for predicting whether a memory access may be a page hit or a page miss and applying different page policies (e.g., an open page policy or a close...
US-9,378,126 Decompression apparatus and decompression method
A decompression apparatus includes a memory configured to store a dictionary data including, in association with a compression code, a decompression symbol and...
US-9,378,125 Semiconductor chip and method of controlling memory
Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The...
US-9,378,124 Software testing optimizer
In an approach for testing software, a computer receives a series of two or more revisions to a set of software code. The computer identifies modifications...
US-9,378,123 Testing of transaction tracking software
In a method for generating test transactions across computing systems, a first test function of a first program on a first computing system of a plurality of...
US-9,378,122 Adopting an existing automation script to a new framework
Arrangements described herein relate to adopting an existing automation script to a new framework. A first version of an automation script configured to execute...
US-9,378,121 Item-level restoration and verification of image level
Systems and methods for item-level restoration from and verification of an image level backup without fully extracting it. The method receives backup parameters...
US-9,378,120 Automated test execution plan derivation system and method
A system and method is disclosed that has the ability to automatically derive a test execution plan for parallel execution of test cases, while considering the...
US-9,378,119 Release template
A project change control record in a release template controls the release of a code change from a change control platform into a test environment. The change...
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