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Integrated clock differential buffering
Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock...
Automated load tracking and system tuning mechanism for wireless charging
A system includes at least one active energy transfer coil and a first passive energy transfer coil. The active energy transfer coil is configured to couple...
Chip and method for manufacturing a chip
According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first...
Runtime loading of configuration data in a configurable IC
Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different...
Methods for operating configurable storage and processing blocks at double
and single data rates
Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and...
CMOS level shifter circuit with self-adaptive local supply boosting for
wide voltage range operation
A level shifter that supports wide voltage range operation by adaptively boosting local supply voltage to its input stage. The level shifter may interface an...
Voltage level shifter circuit
Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In...
Bulk driven low swing driver
A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low...
Semiconductor device and driving method thereof
A semiconductor device in which operation delay can be suppressed is provided. The semiconductor device includes a first logic element, a second logic element,...
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within...
Input-output buffer circuit with a gate bias generator
An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second...
Level-sensitive two-phase single-wire latch controllers without contention
Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R...
A semiconductor device includes a first block coupled between a first latch node and a second latch node, a second block suitable for generating common-mode...
Multi-threshold flash NCL logic circuitry with flash reset
Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption...
Self-leveling logic receiver
Various implementations include circuits, devices and/or methods that provide closed-loop feedback crowbar current limiting for logic level-shifting between...
Logic circuit, processing unit, electronic component, and electronic
A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third...
Impedance and duty cycle calibration in a driver circuit and a receiver
Some of the embodiments of the present disclosure provide a method including: communicating, by a first pin of an integrated circuit, with a device over a...
A switch device includes a housing, a substrate, a single operation knob including an operation plate having operation indications provided thereon and moving...
Touch screen, electronic device comprising same and method for
Embodiments of the present invention provide a touch screen, an electronic device comprising the same and a method for manufacturing the same. The touch screen...
Capacitive distance sensor
A capacitive distance sensor is provided having an elongated sensor element. The sensor element comprises a cylindrical carrier body, which is made of an...
Methodology to avoid gate stress for low voltage devices in FDSOI
An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors...
Multi-gate high voltage device
A high voltage semiconductor device, particularly a device including a number of high breakdown voltage transistors having a common drain, first well, and...
Battery management system with MOSFET boost system
A boost converter for driving the gate of n-channel MOSFET power devices is described. The boost converter includes a monitoring circuit and a kick start...
H-bridge gate control circuit
A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a...
Semiconductor device and driving method of the same
In the case of reducing an effect of variations in current characteristics of transistors by inputting a signal current to a transistor in a pixel, a potential...
Circuit and method for body biasing
Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body...
An input/output (I/O) module is configured to connect a controller and a field device. The I/O module includes a PWM (pulse width modulation) demodulator...
Method and device for generating PWM pulses for multi-level inverter
A method and a device for generating PWM pulses for an inverter are provided. The three-phase inverter's characteristic of including high frequency...
Clock monitoring for sequential logic circuits
A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator...
Delay cell, delay locked look circuit, and phase locked loop circuit
A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first...
Pulse width modulator for high speed digitally controlled voltage
Described is a pulse width modulation architecture for high speed digitally controlled voltage regulator. Described is an apparatus which comprises: a first...
Method and apparatus for cancellation of spurious signals
Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides...
Generating a pulse clock signal based on a first clock signal and a second
Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal...
Offset calibration for low power and high performance receiver
Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset...
Low-power programmable oscillator and ramp generator
A circuit for generating a signal comprising a first transistor having a drain, a gate and a source. A second transistor having a drain, a source and a gate...
Flip-flop circuit and semiconductor apparatus using the same
A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a...
Low power oscillator with charge subtraction scheme
An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme...
Timing control device and control method thereof
Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and...
Integrated circuit with multiplexed I/O pads
An integrated circuit (IC) includes power domains and I/O multiplexing units. The I/O multiplexing units include components that are spilt across the power...
Open loop band gap reference voltage generator
A reference voltage generator that does not require a start-up circuit or a feedback loop generates a proportional-to-absolute-temperature (PTAT) output voltage...
Filter auto-calibration using multi-clock generator
A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal...
Configurable radio frequency attenuator
RF attenuator circuitry includes an RF attenuator and a control system. The RF attenuator is configured to provide an attenuation response between an input node...
Acoustic wave device
An acoustic wave filter includes a piezoelectric substrate, an insulating pattern that has higher thermal conductivity than the piezoelectric substrate formed...
MEMS vibrating structure using an orientation dependent single-crystal
piezoelectric thin film layer
A micro-electrical-mechanical system (MEMS) vibrating structure includes a carrier substrate, a first anchor, a second anchor, a single crystal piezoelectric...
Acoustic resonator having guard ring
A bulk acoustic wave (BAW) resonator structure comprises a first electrode disposed over a substrate, a piezoelectric layer disposed over the first electrode, a...
Diplexer and transceiver thereof
A diplexer, for coupling a first radio frequency (RF) signal corresponding to a first carrier frequency and a second RF signal corresponding to a second carrier...
High frequency component and filter component
A high frequency component includes a multilayer body including a plurality of insulating layers stacked in a stacking direction, linear conductors extending...
An HF-line includes parallel branches with bias terminals, to which a direct voltage source is respectively connected via a first inductor and a second...
Crest factor reduction applied to shaping table to increase power
amplifier efficiency of envelope tracking...
There is disclosed a method of controlling an input to an envelope modulated power supply of an envelope tracking amplification stage, comprising: generating an...
Staggered Y topology for multiband limiter
A multiband limiter with Staggered-Y topology including a band splitter having a signal input and a plurality of bands, a first band limiter having an input...