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Patent # Description
US-9,385,121 Tipless transistors, short-tip transistors, and methods and circuits therefor
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one...
US-9,385,120 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device is provided. A sacrificial gate, a hard mask, a spacer and a first interlayer insulating film are formed on a...
US-9,385,119 Semiconductor arrangement with a load, a sense and a start-up transistor
A semiconductor arrangement includes a semiconductor body with a first active region, a second active region and an isolation region arranged between the first...
US-9,385,118 Capacitor array having capacitor cell structures
A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first...
US-9,385,117 NPN heterojunction bipolar transistor in CMOS flow
An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the...
US-9,385,116 Semiconductor ESD device
An electrostatic discharge (ESD) protection device on a semiconductor substrate and a method for making the same. The device has an active region. The active...
US-9,385,115 Electrostatic discharge protection device
The present disclosure relates to an electrostatic discharge (ESD) protection device. The electrostatic discharge protection device, may comprise: a...
US-9,385,114 Non-linear element, display device including non-linear element, and electronic device including display device
A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor...
US-9,385,113 Semiconductor integrated circuit device
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring...
US-9,385,112 Semiconductor devices
A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first...
US-9,385,111 Electronic component with electronic chip between redistribution structure and mounting structure
An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive...
US-9,385,110 Semiconductor device and method
A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor...
US-9,385,109 Semiconductor packages having trench-shaped opening and methods for fabricating the same
Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package,...
US-9,385,108 Light-emitting device having optoelectronic elements on different elevations
The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting...
US-9,385,107 Multichip device including a substrate
A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the...
US-9,385,106 Method for providing charge protection to one or more dies during formation of a stacked silicon device
A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected...
US-9,385,105 Semiconductor devices
A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally...
US-9,385,104 Bonding apparatus
Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the...
US-9,385,103 Semiconductor device manufacturing method
A method for manufacturing a semiconductor device, includes preparing a solder, a soldering article, a base material, a weight having a foot where a center of...
US-9,385,102 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level...
A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a...
US-9,385,101 Semiconductor device and method of forming bump-on-lead interconnection
A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a...
US-9,385,100 Integrated circuit packaging system with surface treatment and method of manufacture thereof
An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a...
US-9,385,099 Die interconnect
One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid...
US-9,385,098 Variable-size solder bump structures for integrated circuit packaging
An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality...
US-9,385,097 Bump-on-trace methods and structures in packaging
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a...
US-9,385,096 Semiconductor device with bumps and display device module incorporating the same
A semiconductor device includes: a semiconductor chip having a main face which has a pair of long sides parallel to each other and a pair of short sides...
US-9,385,095 3D semiconductor package interposer with die cavity
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or...
US-9,385,094 Apparatus, system, and method for wireless connection in integrated circuit packages
Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of...
US-9,385,093 Chip diode and diode package
A chip diode includes a plurality of diode cells formed on a semiconductor substrate, each having a diode junction region; and parallel connection portions...
US-9,385,092 Semiconductor device, electronic device and method for fabricating the semiconductor device
A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has...
US-9,385,091 Reinforcement structure and method for controlling warpage of chip mounted on substrate
A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the...
US-9,385,090 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering...
US-9,385,089 Alignment mark recovery with reduced topography
When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of...
US-9,385,088 3D semiconductor device and structure
A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second...
US-9,385,087 Polysilicon resistor structure having modified oxide layer
Various embodiments include resistor structures. Particular embodiments include a resistor structure having multiple oxide layers, at least one of which...
US-9,385,086 Bi-layer hard mask for robust metallization profile
A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in...
US-9,385,085 Interconnects with fully clad lines
A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein...
US-9,385,084 Metal pattern structure having positioning layer
A metal pattern structure having a positioning layer thereon is provided. The positioning layer is located within a predetermined region of the metal pattern...
US-9,385,083 Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink...
US-9,385,082 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to...
US-9,385,081 Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same
A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e.,...
US-9,385,080 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate;...
US-9,385,079 Methods for forming stacked capacitors with fuse protection
An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry...
US-9,385,078 Self aligned via in integrated circuit
A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic...
US-9,385,077 Integrated device comprising coaxial interconnect
Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect...
US-9,385,076 Semiconductor device with bump structure on an interconncet structure
A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and...
US-9,385,075 Glass carrier with embedded semiconductor device and metal layers on the top surface
A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from...
US-9,385,074 Semiconductor package with embedded die
A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the...
US-9,385,073 Packages having integrated devices and methods of forming same
An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface...
US-9,385,072 Method of manufacturing semiconductor device and semiconductor device
Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor...
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