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Patent # Description
US-9,385,071 Manufacturing method of semiconductor device and semiconductor device
A semiconductor device includes a die pad, which includes an upper surface and a lower surface opposite to the upper surface, the upper surface forming a...
US-9,385,070 Semiconductor component having a lateral semiconductor device and a vertical semiconductor device
A semiconductor component comprising a lateral semiconductor device, a vertical semiconductor device, and a leadframe is provided. The lateral semiconductor...
US-9,385,069 Gate contact structure for FinFET
An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions...
US-9,385,068 Stacked interconnect structure and method of making the same
A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a...
US-9,385,067 Semiconductor device with through silicon via and alignment mark
A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected...
US-9,385,066 Integrated circuit packaging system with molded laser via interposer and method of manufacture thereof
A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an...
US-9,385,065 Solid state thermal rectifier
Thermal rectifiers using linear nanostructures as core thermal conductors have been fabricated. A high mass density material is added preferentially to one end...
US-9,385,064 Heat sink having a through-opening
A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a...
US-9,385,063 Thermally conductive sheet feeder and method for feeding thermally conductive sheet
Provided by the present invention are a thermally conductive sheet feeder and a method for feeding a thermally conductive sheet, which are a thermally...
US-9,385,062 Integrated circuit barrierless microfluidic channel
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
US-9,385,061 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes: semiconductor modules in which a circuit board having at least one or more semiconductor chips mounted thereon is sealed with a...
US-9,385,060 Integrated circuit package with enhanced thermal conduction
Integrated circuit packages with enhanced thermal conduction are disclosed. A disclosed integrated circuit package includes a package substrate. An integrated...
US-9,385,059 Overmolded substrate-chip arrangement with heat sink
An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system...
US-9,385,058 Semiconductor device and structure
An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one...
US-9,385,057 Semiconductor device
A semiconductor flat package has a semiconductor chip, leads connected to the semiconductor chip, and an encapsulation resin covering the semiconductor chip and...
US-9,385,056 Packaging substrate having embedded interposer and fabrication method thereof
A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a...
US-9,385,055 Stacked semiconductor chips with thermal management
A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a...
US-9,385,054 Data processing device and manufacturing method thereof
A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M...
US-9,385,053 Method and apparatus for semiconductor testing at low temperature
A method for testing a plurality of semiconductor devices arranged on a strip may include forming an array of semiconductor devices on a frame, wherein contact...
US-9,385,052 Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim...
A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after...
US-9,385,051 Method for the formation of a FinFET device having partially dielectric isolated fin structure
A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over...
US-9,385,050 Structure and method to fabricate resistor on finFET processes
A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented...
US-9,385,049 Process for manufacturing integrated device incorporating low-voltage components and power components
An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI...
US-9,385,048 Method of forming Fin-FET
The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins...
US-9,385,047 Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel...
Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same...
US-9,385,046 Voids in STI regions for forming bulk FinFETs
An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at...
US-9,385,045 Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
US-9,385,044 Replacement gate process
An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer...
US-9,385,043 Spacer enabled poly gate
A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed...
US-9,385,042 Semiconductor device
This invention provides a technique advantageous to improve the operating speed of an integrated circuit. In a semiconductor device in which an n-type...
US-9,385,041 Method for insulating singulated electronic die
In one embodiment, a method of forming an electronic device includes providing a wafer having plurality of die separated by spaces. The method includes plasma...
US-9,385,040 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes providing a wafer, grinding a backside of the wafer, disposing a backside film on the backside of the...
US-9,385,039 Formation of through-silicon via (TSV) in silicon substrate
To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an...
US-9,385,038 Selective local metal cap layer formation for improved electromigration behavior
A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD);...
US-9,385,037 Semiconductor arrangement comprising metal cap and dielectric layer defining air gap
One or more semiconductor arrangements are provided. A semiconductor arrangement includes a first dielectric layer defining a first recess, a first contact in...
US-9,385,036 Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an...
US-9,385,035 Current ramping and current pulsing entry of substrates for electroplating
In some method and apparatus disclosed herein, the profile of current delivered to the substrate provides a relatively uniform current density on the substrate...
US-9,385,034 Carbonization of metal caps
An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric...
US-9,385,033 Method of forming a metal from a cobalt metal precursor
A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein...
US-9,385,032 Systems and methods involving data bus inversion memory circuitry, configuration and/or operation
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation,...
US-9,385,031 Method for providing a self-aligned pad protection in a semiconductor device
According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over...
US-9,385,030 Spacer to prevent source-drain contact encroachment
Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be...
US-9,385,029 Method for forming recess-free interconnect structure
A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over...
US-9,385,028 Air gap process
Methods are described for forming "air gaps" between adjacent metal lines on patterned substrates. The common name "air gap" will be used interchangeably with...
US-9,385,027 Sublithographic Kelvin structure patterned with DSA
In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines...
US-9,385,026 Sublithographic Kelvin structure patterned with DSA
In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines...
US-9,385,025 E-fuses containing at least one underlying tungsten contact for programming
Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is...
US-9,385,024 Room temperature metal direct bonding
A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a...
US-9,385,023 Method and structure to make fins with different fin heights and no topography
A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process...
US-9,385,022 Silicon waveguide on bulk silicon substrate and methods of forming
Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions...
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