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Patent # Description
US-9,384,821 Row hammer monitoring based on stored row hammer threshold value
Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data...
US-9,384,820 Aligning calibration segments for increased availability of memory subsystem
A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem...
US-9,384,819 Semiconductor device latching data signal in response to strobe signal and information processing system...
Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that...
US-9,384,818 Memory power management
A memory system is described, where a plurality of memory modules is connected to a memory controller. The power status of each of the memory modules is...
US-9,384,817 Refresh signal generation circuit and semiconductor device using the same
This technology includes: a refresh signal generation unit configured to generate a first preliminary refresh signal with a cycle varying according to...
US-9,384,816 Semiconductor memory device and method for driving the same
In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit...
US-9,384,815 Mechanisms for preventing leakage currents in memory cells
Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first...
US-9,384,814 Thyristor memory and methods of operation
Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is...
US-9,384,813 Semiconductor device applicable to a multi-context programmable logic device
A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the...
US-9,384,812 Three-phase GSHE-MTJ non-volatile flip-flop
Systems and methods are directed to a three-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect...
US-9,384,811 Method and system for providing a thermally assisted spin transfer torque magnetic device including smart...
A magnetic device usable in electronic devices is described. The magnetic device includes a magnetic junction and at least one smart thermal barrier that is...
US-9,384,810 Monolithic multi-channel adaptable STT-MRAM
A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes...
US-9,384,809 Word line divider and storage device
A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and...
US-9,384,808 Address input circuit of semiconductor apparatus
An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially...
US-9,384,807 Parameter setting circuit and semiconductor apparatus using the same
A parameter setting circuit includes a first parameter setting unit configured to set a first parameter using first code signals generated by adjusting a value...
US-9,384,806 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of...
A memory device includes a plurality of memory layers and a selecting circuit configured to select a delta value corresponding to a parameter of at least one of...
US-9,384,805 Semiconductor memory device, semiconductor system and test method thereof
A semiconductor memory device may include a control signal generation unit suitable for generating a block selection signal in response to first and second...
US-9,384,804 Semiconductor device and semiconductor system
A semiconductor system is provided, which includes a controller configured to output an active command and test mode signals; and a semiconductor device...
US-9,384,803 Storage device and latch management method thereof
A latch management method of a storage device includes permitting the storage device to enter a reduced power mode in which the storage device operates with a...
US-9,384,802 Bit line sensing methods of memory devices
Bit line sensing methods may be provided. The methods may include pre-charging a first bit line and a second bit line with a bit line pre-charge voltage. The...
US-9,384,801 Threshold voltage expansion
Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically,...
US-9,384,800 Semiconductor device and semiconductor system having the same
A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command,...
US-9,384,799 Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and...
US-9,384,798 Semiconductor memory device
A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a...
US-9,384,797 Memory control method and system
A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the...
US-9,384,796 Semiconductor memory device and memory system including the same
A semiconductor memory device includes a core region for storing data and a peripheral region for controlling the core region. The semiconductor memory device...
US-9,384,795 Fully valid-gated read and write for low power array
In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read...
US-9,384,794 Semiconductor device and method of operating the same
A semiconductor device includes a pipeline latch unit including a plurality of write pipelines, and suitable for latching data, and a control unit suitable for...
US-9,384,793 Dynamic granule-based intermediate storage
A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data...
US-9,384,792 Offset-cancelling self-reference STT-MRAM sense amplifier
Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the...
US-9,384,791 Apparatus and method for sense amplifier offset cancellation
Disclosed is a circuit architecture for cancellation of threshold voltage offsets for an array of sense amplifiers. An offset calibration controller, which may...
US-9,384,790 Memory device with separately controlled sense amplifiers
A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and...
US-9,384,789 Power management in an electronic system through reducing energy usage of a battery and/or controlling an...
A method includes configuring a battery and a voltage regulator configured to regulate an output voltage of the battery to supply power to a memory of an...
US-9,384,788 Multilayered semiconductor device
A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip,...
US-9,384,787 Selecting a voltage sense line that maximizes memory margin
A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method...
US-9,384,786 Power management in an electronic system through reducing energy usage of a battery and/or controlling an...
A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage...
US-9,384,785 Multi-channel memory and power supply-driven channel selection
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels...
US-9,384,784 Data synchronous reproduction apparatus, data synchronous reproduction method, and data synchronization control...
A data synchronous reproduction apparatus capable of synchronously reproducing image frames and numerical data at high speed, including: a data storage section...
US-9,384,783 Editing method and recording and reproducing device
In order to provide a recording and reproducing device that allows a user to select and manage arbitrary play lists, a unit of management for managing all...
US-9,384,782 Record file editing method and system
The present invention is applicable to the field of multimedia technologies and provides a record file editing method and system, where the method includes:...
US-9,384,781 Method of sparse representation of contents of high-resolution video images supporting content editing and...
This invention provides a method of sparse representation of contents of high-resolution video images which supports content editing and propagation. It mainly...
US-9,384,780 System and method for video summarization and navigation based on statistical models
The disclosed method calculates video time density functions based on inter-frame mutual information or other similarity measures. The method includes acquiring...
US-9,384,779 Information storage device with multiple-use fields in servo pattern
An embodiment of the present invention implements some or all major servo subfunctions for a storage device in integrated servo fields comprising sequences of...
US-9,384,778 Online iteration resource allocation for large sector format drive
Systems and methods for resource allocation for a large sector format processing may include, but are not limited to, operations for: determining...
US-9,384,777 Efficient elimination of access to data on a writable storage media
A system provided for eliminating access to data within a writable storage media cartridge. The system comprises a writable storage media drive, such as a tape...
US-9,384,776 Clamping device of spindle motor including case having inclination surface
The clamping device of spindle motor is disclosed, wherein a case portion contacted by the other distal end of the arms is inclined due to depression of a...
US-9,384,775 Ratcheting gripper for a storage library
Embodiments of the invention include systems and methods for selective gripping and/or releasing of media cartridges using a robotic ratcheting gripper...
US-9,384,774 Data storage device calibrating a laser power for heat assisted magnetic recording based on slope of quality metric
A data storage device is disclosed comprising a disk and a head actuated over the disk, wherein the head comprises a laser configured to heat the disk while...
US-9,384,773 Annealing treatment for ion-implanted patterned media
The present disclosure relates to a method for fabricating an ion-implanted bit-patterned medium. The method includes providing a medium, the medium having a...
US-9,384,772 Magnetic recording medium having L1.sub.0 magnetic layer and plurality of underlayers, and magnetic storage...
A magnetic recording medium includes a substrate, a magnetic layer including an alloy having a L1.sub.0 type crystal structure as a main component thereof, and...
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