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Patent # Description
US-9,384,169 Numerical method for solving an inverse problem in subsonic flows
It is a numerical method for solving an inverse problem about the shape design of aerodynamic body in inviscid subsonic flows. This method transfers the...
US-9,384,168 Vector matrix product accelerator for microprocessor integration
In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus...
US-9,384,167 Formal verification of booth multipliers
Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be...
US-9,384,166 Vehicular input device and vehicular input method
An object of the present invention is to provide a vehicular input device which is capable of improving accuracy for detecting a contactless input from a...
US-9,384,165 Configuring routing in mesh networks
A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and...
US-9,384,164 Mapping memory controller connectors to memory connectors
Provided are a device, system, and method for mapping memory controller connectors to memory connectors. A memory is programmed to transmit for each of a...
US-9,384,163 Non-linear termination for an on-package input/output architecture
An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The...
US-9,384,162 Mobile device, transaction system including the mobile device, and method of signal transmission in a mobile device
A mobile device includes a baseband module, an electronic card slot and a control module. A control unit of the control module is configured to control a...
US-9,384,161 Method for data throughput improvement in open core protocol based interconnection networks using dynamically...
Methods and apparatus for facilitating data throughput improvements in interconnect fabrics employing point-to-point links using dynamically selectable routing....
US-9,384,160 Methods and controllers for affiliation managment
Methods and systems for managing Serial Advanced Technology Attachment ("SATA") affiliation transfers between a requesting controller and a granting controller...
US-9,384,159 Creating a checkpoint for a software partition in an asynchronous input/output environment
A computer implemented method, apparatus, and computer program product for creating a checkpoint for a software partition. A checkpoint request is received for...
US-9,384,158 Dynamic universal port mode assignment
Embodiments include a system for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router...
US-9,384,157 Intercomponent data communication
A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is...
US-9,384,156 Support for IOAPIC interrupts in AMBA-based devices
One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP)...
US-9,384,155 Customization of a bus adapter card
The present disclosure includes systems and techniques relating to customization of a bus adapter card. in some implementations, an apparatus includes a...
US-9,384,154 Method to emulate message signaled interrupts with multiple interrupt vectors
Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory...
US-9,384,153 Virtualized local storage
Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory...
US-9,384,152 Coordinating memory operations using memory-device generated reference signals
A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference...
US-9,384,151 Unified SCSI target management for managing a crashed service daemon in a deduplication appliance
Systems and methods are described that manage service daemons using a unified small computer system interface (SCSI) target management daemon. SCSI target...
US-9,384,150 Method and apparatus for performing transparent mass storage backups and snapshots
The present invention relates to providing security functionality over computer system mass storage data, and more particularly relates to a system and method...
US-9,384,149 Block-level data storage security system
A secure storage appliance is disclosed, along with methods of storing and reading data in a secure storage network. The secure storage appliance is configured...
US-9,384,148 Detection of unauthorized memory modification and access using transactional memory
Technologies for detecting unauthorized memory accesses include a computing device having transactional memory support. The computing device executes a code...
US-9,384,147 System and method for cache entry aging
A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that...
US-9,384,146 Dynamic reservations in a unified request queue
A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally...
US-9,384,145 Systems and methods for implementing dynamically configurable perfect hash tables
Hardware circuitry may evaluate minimal perfect hash functions mapping keys to addresses in lookup tables. The circuitry may include primary hash function...
US-9,384,144 Error detection using a logical address key
A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the...
US-9,384,143 Selecting cache lists indicating tracks in a cache to process for demotion
Provided are a computer program product, system, and method for selecting cache lists indicating tracks in a cache to process for demotion. In response to a...
US-9,384,142 Efficient and consistent para-virtual I/O system
Embodiments of the invention relate to a para-virtual I/O system. A consistent para-virtual I.O system architecture is provided with a new virtual disk...
US-9,384,141 Multi-core fuse decompression mechanism
An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a...
US-9,384,140 Apparatus and method for storage and decompression of configuration data
An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled...
US-9,384,139 Maintaining a system state cache
Methods, apparatuses and computer software products implement embodiments of the present invention that include storing, to a module memory in each of a...
US-9,384,138 Temporal tracking of cache data
A data storage system with a cache organizes cache windows into lists based on the number of cache lines accessed during input/output operations. The lists are...
US-9,384,137 Progressive pre-caching
A system includes a computerized appliance connected to a network, a processor, a persistent memory, a dynamic random access memory, and software executing on...
US-9,384,136 Modification of prefetch depth based on high latency event
A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data...
US-9,384,135 System and method of caching hinted data
The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system...
US-9,384,134 Persistent memory for processor main memory
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
US-9,384,133 Synchronizing updates of page table status indicators and performing bulk operations
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page...
US-9,384,132 Emulated message signaled interrupts in a virtualization environment
A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache...
US-9,384,131 Systems and methods for accessing cache memory
Systems and methods for providing data from a cache memory to requestors includes a number of cache memory levels arranged in a hierarchy. The method includes...
US-9,384,130 Rewriting symbol address initialization sequences
A system includes a memory to store a linker and one or modules, and a processor, communicatively coupled to the memory. The computer system is configured to...
US-9,384,129 Garbage collection based on total resource usage and managed object metrics
A method includes selectively controlling, at a computing device having a memory, initiation of a full garbage collection operation based on a total resource...
US-9,384,128 Multi-level redundancy code for non-volatile memory controller
In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before...
US-9,384,127 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A...
US-9,384,126 Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage...
The various implementations described herein include systems, methods and/or devices used to avoid false negative results in Bloom filters implemented in...
US-9,384,125 Method for accessing flash memory having pages used for data backup and associated memory device
The present invention provides a method for accessing a flash memory, where a block of the flash memory includes pages whose quantity is (2.sup.N+M), N and M...
US-9,384,124 Data storage device, memory control method, and electronic device with data storage device
According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a...
US-9,384,123 Memory system
According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile...
US-9,384,122 High sampling rate sensor buffering in semiconductor processing systems
Embodiments of the invention are directed toward systems and/or methods that buffer data from various sensors with a high sampling rate in a semiconductor...
US-9,384,121 Functional test automation for gesture-based mobile applications
A method for cloud-based functional testing of a mobile application includes running a functional test program on a server. The functional test program provides...
US-9,384,120 Testing of transaction tracking software
In a method for generating test transactions across computing systems, a first test function of a first program on a first computing system of a plurality of...
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