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Patent # Description
US-9,391,023 Method for producing salicide and a carbon nanotube metal contact
A method for producing a metal contact in a semiconductor device is disclosed. The method comprises depositing a catalyst layer in a via hole, forming a...
US-9,391,022 Semiconductor device and a method of manufacturing the same
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is...
US-9,391,021 Chip package and method for fabricating the same
A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a...
US-9,391,020 Interconnect structure having large self-aligned vias
A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a...
US-9,391,019 Scalable interconnect structures with selective via posts
Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to...
US-9,391,018 Crosstalk polarity reversal and cancellation through substrate material tuning
Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane....
US-9,391,017 Semiconductor integrated circuit
In one embodiment, a semiconductor integrated circuit includes power supply strap wires extending in a first direction in a first layer, auxiliary power supply...
US-9,391,016 MIM capacitor structure
The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments,...
US-9,391,015 Method for forming a three-dimensional structure of metal-insulator-metal type
A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the...
US-9,391,014 Physical unclonable interconnect function array
A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over...
US-9,391,013 3D integrated circuit package with window interposer
3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package...
US-9,391,012 Methods and apparatus for package with interposers
Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality...
US-9,391,011 Semiconductor structures including fluidic microchannels for cooling and related methods
Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the...
US-9,391,010 Power line filter for multidimensional integrated circuits
An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through...
US-9,391,009 Semiconductor packages including heat exhaust part
According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each...
US-9,391,008 Reconstituted wafer-level package DRAM
A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and...
US-9,391,007 Built-up lead frame QFN and DFN packages and method of making thereof
Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The...
US-9,391,006 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an...
US-9,391,005 Method for packaging a power device with bottom source electrode
A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side...
US-9,391,004 Power semiconductor package with conductive clip and related method
A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can,...
US-9,391,003 Semiconductor package with conductive clip
A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can,...
US-9,391,002 Semiconductor sensor chips
Semiconductor sensor chips are provided. In some embodiments, a semiconductor sensor chip can include at least one wire bond pad on one side thereof, at least...
US-9,391,001 Semiconductor constructions
Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection....
US-9,391,000 Methods for forming silicon-based hermetic thermal solutions
A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the...
US-9,390,999 Metal substrate/metal impregnated carbon composite material structure and method for manufacturing said structure
Provided are a heat releasing material for an electronic device being manufactured by the junction of a metal impregnated carbon composite material on a copper...
US-9,390,998 Heat spreading substrate
Heat spreading substrate. In accordance with an embodiment of the present invention, an apparatus includes a thermally conductive, electrically insulating...
US-9,390,997 Semiconductor chip and stacked type semiconductor package having the same
The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip...
US-9,390,996 Double-sided cooling power module and method for manufacturing the same
A double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at least...
US-9,390,995 Semiconductor device and method of manufacturing the same
An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good...
US-9,390,994 Heat sinks with interdigitated heat pipes
A chip package includes adjacent integrated circuits on a circuit board, and separate heat sinks are thermally coupled to the integrated circuits. Because the...
US-9,390,993 Semiconductor border protection sealant
A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads...
US-9,390,992 Semiconductor packages including a metal layer between first and second semiconductor chips
Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the...
US-9,390,991 Semiconductor device and method of forming wafer level ground plane and power ring
A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the...
US-9,390,990 Molding composition for semiconductor package and semiconductor package using the same
Disclosed herein are a molding composition for a semiconductor package including a liquid crystal thermosetting polymer resin and graphene oxide to thereby...
US-9,390,989 Enhanced modularity in heterogeneous 3D stacks
A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code...
US-9,390,988 Method for soldering a cap to a support layer
One embodiment discloses a method for soldering a cap for an integrated electronic device to a support layer, including the steps of: providing a support layer;...
US-9,390,987 Semiconductor module including a terminal embedded in casing wall and bent over thick portion of lid
Aspects of the invention provide a semiconductor module that can be manufactured without using a bending jig for bearing the stress in bending process of the...
US-9,390,986 Polishing apparatus and polishing method
A polishing apparatus capable of achieving a good control operation for a distribution of remaining film thickness is disclosed. The polishing apparatus...
US-9,390,985 Semiconductor arrangement and formation thereof
Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second...
US-9,390,984 X-ray inspection of bumps on a semiconductor substrate
A method for inspection includes irradiating, with a focused beam, a feature formed on a semiconductor wafer, the feature including a volume containing a first...
US-9,390,983 Semiconductor device and method for fabricating the same
A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a...
US-9,390,982 CMOS devices with reduced leakage and methods of forming the same
A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second...
US-9,390,981 Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect...
In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate...
US-9,390,980 III-V compound and germanium compound nanowire suspension with germanium-containing release layer
A device that includes: a substrate layer; a first set of source/drain component(s) defining an nFET (n-type field-effect transistor) region; a second set of...
US-9,390,979 Opposite polarity borderless replacement metal contact scheme
An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of...
US-9,390,978 Method for producing semiconductor device and semiconductor device
A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second...
US-9,390,977 Method for manufacturing a fin=shaped field effect transistor capable of reducing a threshold voltage variation
A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on...
US-9,390,976 Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
A method of forming a semiconductor device that includes forming a fin structure, and forming an undoped epitaxial semiconductor material on the fin structure....
US-9,390,975 Methods for producing a tunnel field-effect transistor
A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning...
US-9,390,974 Back-to-back stacked integrated circuit assembly and method of making
An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with...
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