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Patent # Description
US-9,390,973 On-chip RF shields with backside redistribution lines
Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes...
US-9,390,972 Method of fabricating semiconductor device including a substrate having copper interconnects
A method of fabricating a semiconductor device including a substrate having a copper interconnect exposed on a surface of an insulation film, wherein a layer of...
US-9,390,971 Self-aligned barrier and capping layers for interconnects
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing...
US-9,390,970 Method for depositing a diffusion barrier layer and a metal conductive layer
We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which...
US-9,390,969 Integrated circuit and interconnect, and method of fabricating same
The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance...
US-9,390,968 Low temperature thin wafer backside vacuum process with backgrinding tape
Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the...
US-9,390,967 Method for residue-free block pattern transfer onto metal interconnects for air gap formation
A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect...
US-9,390,966 Methods of forming wiring structures and methods of fabricating semiconductor devices
Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating...
US-9,390,965 Air-gap forming techniques for interconnect structures
An interconnect structure includes a first low-k dielectric layer formed over a substrate. A first metal line is disposed in the first low-k dielectric layer....
US-9,390,964 Methods for fabricating dual damascene structures in low temperature dielectric materials
Methods for fabricating dual damascene structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may...
US-9,390,963 Semiconductor memory device
A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in...
US-9,390,962 Methods for fabricating device substrates and integrated circuits
Methods for fabricating device substrates are provided where the device substrates have rounded trench corners in medium voltage (MV) and high voltage (HV)...
US-9,390,961 Semiconductor devices having plug insulators
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first...
US-9,390,960 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first...
US-9,390,959 Semiconductor package with stator set formed by circuits
A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface...
US-9,390,958 Transfer unit including suction openings configured to receive suction pads or seal members therein
A transfer unit transferring a wafer from or to a cassette is provided. The transfer unit includes a holding portion holding the wafer under suction and a...
US-9,390,957 Substrate transfer apparatus and method, and substrate processing apparatus
Provided are a substrate transfer apparatus and method and a substrate processing apparatus. The substrate transfer apparatus includes: a body portion; an arm...
US-9,390,956 Method for the temporary connection of a product substrate to a carrier substrate
A method for temporary connection of a product substrate to a carrier substrate comprised of the steps of: applying an interconnect layer to a product...
US-9,390,955 Handle substrate and composite wafer for semiconductor device
In a handle substrate for a composite wafer for a semiconductor, particles from the wafer with a notch formed therein are reduced. The handle substrate 1A or 1B...
US-9,390,954 Substrate transfer robot, substrate transfer system, and method for detecting arrangement state of substrate
A substrate transfer robot includes a hand and a controller. The hand includes at least one detector configured to detect an arrangement state of a substrate in...
US-9,390,953 Substrate damage detection device, substrate transfer robot with substrate damage detection device, and...
A substrate damage detection device is configured to be mounted to a substrate transfer robot provided with a slidably-movable substrate support. The substrate...
US-9,390,952 Device and method for loading and unloading quartz reaction tube to and from semiconductor diffusion equipment
A loading and unloading device and method for a quartz reaction tube of a semiconductor diffusion equipment are provided; the loading and unloading device is...
US-9,390,951 Methods and systems for electric field deposition of nanowires and other devices
Methods, systems, and apparatuses for nanowire deposition are provided. A deposition system includes an enclosed flow channel, an inlet port, and an electrical...
US-9,390,950 Rapid thermal processing chamber with micro-positioning system
Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an...
US-9,390,949 Wafer debonding and cleaning apparatus and method of use
This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a...
US-9,390,948 Tape attaching apparatus and tape attaching method
A tape attaching apparatus includes: a chamber having an airtight space formed therein; a rubber sheet that partitions the airtight space into first and second...
US-9,390,947 Thermal processing method and thermal processing apparatus for heating substrate, and susceptor
A semiconductor wafer with (100) plane orientation has two orthogonal cleavage directions. A notch is provided so as to indicate one of these directions. During...
US-9,390,946 Cleaning apparatus
A cleaning apparatus including a holding table for holding a plate-shaped workpiece, a cleaning nozzle for spraying a cleaning fluid to the plate-shaped...
US-9,390,945 Semiconductor device and method of depositing underfill material with uniform flow rate
A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the...
US-9,390,944 Electrical connectivity for circuit applications
According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed...
US-9,390,943 Substrate processing apparatus
A substrate processing apparatus generates an electric field in a processing space between a lower electrode to which a high frequency power is supplied and an...
US-9,390,942 Method, system, and apparatus for preparing substrates and bonding semiconductor layers to substrates
Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals...
US-9,390,941 Sample processing apparatus, sample processing system, and method for processing sample
There is provided a VUV light processing apparatus that can apply vacuum ultraviolet light to the entire surface of a wafer in excellent reproducibility and can...
US-9,390,940 Methods of etching films comprising transition metals
Provided are methods for etching films comprising transition metals. Certain methods involve activating a substrate surface comprising at least one transition...
US-9,390,939 Methods of forming MIS contact structures for semiconductor devices and the resulting devices
One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact...
US-9,390,938 Polishing composition
To provide a means by which polishing rate can further be improved in a polishing composition to be used for an application of polishing an object to be...
US-9,390,937 Silicon-carbon-nitride selective etch
A method of etching exposed silicon-nitrogen-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch...
US-9,390,936 Methods for fabricating high aspect ratio probes and deforming high aspect ratio nanopillars and micropillars
Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and...
US-9,390,935 Etching method
Provided is an etching method for forming a space with an aspect ratio of 50 or more in a workpiece including a silicon oxide film and a hard mask. The etching...
US-9,390,934 Phase shift mask, method of forming asymmetric pattern, method of manufacturing diffraction grating, and method...
A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor...
US-9,390,933 Etching method, storage medium and etching apparatus
There is a method of selectively etching a silicon oxide film among a silicon nitride film and the silicon oxide film formed on a surface of a substrate to be...
US-9,390,932 Electropositive metal containing layers for semiconductor applications
Embodiments of the present invention provide methods for forming layers that comprise electropositive metals through ALD (atomic layer deposition) and or CVD...
US-9,390,931 Manufacturing method of strip-shaped conductive structures and non-volatile memory cell
A manufacturing method of floating gate is disclosed. A substrate having a plurality of isolation structures is provided, and top surfaces of the isolation...
US-9,390,930 Surface stabilization process to reduce dopant diffusion
A method for incorporating radicals of a plasma into a substrate or a material on a semiconductor substrate using a remote plasma source. In one embodiment, a...
US-9,390,929 CMOS image sensor
A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage...
US-9,390,928 Anisotropic dielectric material gate spacer for a field effect transistor
Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling...
US-9,390,927 Contact formation for split gate flash memory
An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes...
US-9,390,926 Process sheet resistance uniformity improvement using multiple melt laser exposures
Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser...
US-9,390,925 Silicon--germanium (SiGe) fin formation
Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure...
US-9,390,924 Method for manufacturing SiC substrate
A method for manufacturing a SiC substrate is provided. The method includes: a sacrificial film-forming process of forming a sacrificial film on a surface of a...
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