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Patent # Description
US-9,390,823 Radiation image acquiring device
There is provided is a radiation image acquiring device which corrects a positional displacement between a collimator and a detector and obtains an image...
US-9,390,822 Oxidation decontamination reagent for removal of the dense radioactive oxide layer on the metal surface and...
The present invention provides an oxidative decontamination reagent for removal of the dense radioactive oxide layer on a metal surface, which comprises an...
US-9,390,821 Gripper mechanism
A gripper mechanism for moving an object having a surface cavity, the gripper mechanism comprising an actuation end moveable in an axial direction and a rotary...
US-9,390,820 Electricity production module
An underwater electricity production module includes an elongated cylindrical box, which includes a reactor compartment, which further includes a reservoir...
US-9,390,819 Submerged energy production module
An underwater electricity production module includes an elongated cylindrical box, which includes a reactor compartment and an electricity generator...
US-9,390,818 Underwater electricity production module
The underwater electricity production module according to the invention includes means in the form of an elongated cylindrical box (12) in which means are...
US-9,390,817 Fuel assembly for a pressurized water reactor
A fuel assembly for a pressurized water nuclear reactor includes a multiplicity of fuel rods which extend in a longitudinal direction and are guided in a...
US-9,390,816 Integrated circuit having voltage mismatch reduction
An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first...
US-9,390,815 Semiconductor system and method for testing semiconductor device
A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address...
US-9,390,814 Fault detection and prediction for data storage elements
A circuit, configured to detect faults in an array of data storage elements, comprises: a resistor network; a switching network for selectively coupling a...
US-9,390,813 Shift register including unit circuits connected in multistage manner, and display device
A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output...
US-9,390,812 E-fuse test device and semiconductor device including the same
An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first...
US-9,390,811 Semiconductor device with fuse array and method for operating the same
A semiconductor device includes a fuse array including verification fuses and normal fuses, a determination block suitable for reading data programmed in the...
US-9,390,810 Semiconductor device and control method thereof
In an OTP memory storing a one-bit of the data by two gate insulating film destruction type nonvolatile memory cells where a same bit line is connected and...
US-9,390,809 Data storage in a memory block following WL-WL short
A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage...
US-9,390,808 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell transistor and a word line connected to the memory cell transistor. A...
US-9,390,807 Erase method for flash
An erase method for a flash memory is provided. First memory cells of the flash memory are pre-programmed. The first memory cells are disposed in a memory array...
US-9,390,806 Memory system and method of operating the same
A memory system includes a memory device, a plurality of memory blocks which include a plurality of memory cells electrically coupled to a plurality of word...
US-9,390,805 Memory systems and operating methods of memory controllers
A memory system is provided which includes a nonvolatile memory; and a controller configured to control the nonvolatile memory, wherein the controller comprises...
US-9,390,804 Flash memory counter
A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least...
US-9,390,803 Non-volatile memory devices, operating methods thereof and memory systems including the same
Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a...
US-9,390,802 Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit...
US-9,390,801 Secure memory which reduces degradation of data
A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a...
US-9,390,800 Semiconductor memory and semiconductor memory control method
According to one embodiment, a semiconductor memory includes memory cells, word lines connected to gate of memory cells arranged in a row direction, a control...
US-9,390,799 Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells
Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first...
US-9,390,798 1T-1R architecture for resistive random access memory
A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled...
US-9,390,797 Driving method of variable resistance element and non-volatile memory device
A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to...
US-9,390,796 Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The...
US-9,390,794 Semiconductor device and operating method thereof
A semiconductor device may include a candidate selector configured for generating a plurality of candidate threshold value sets from a plurality of digital...
US-9,390,793 Leakage current compensation with reference bit line sensing in non-volatile memory
A non-volatile memory includes a sense amplifier that uses a reference bit line. The sense amplifier includes a first capacitor coupled to a selected bit line...
US-9,390,792 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-9,390,791 Resistance change non-volatile storage memory device and method
A data recording method includes recording data in memory cells on the basis of whether each memory cell is in an initial state or a variable state. The...
US-9,390,790 Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select...
The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change...
US-9,390,789 Semiconductor storage device having an SRAM memory cell and control and precharge circuits
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is...
US-9,390,788 Configurable delay circuit and method of clock buffering
An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically...
US-9,390,787 Biasing bulk of a transistor
A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The...
US-9,390,786 Method of minimizing the operating voltage of an SRAM cell
An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an...
US-9,390,785 Method, apparatus and system for determining a write recovery time of a memory based on temperature
Techniques and mechanisms for determining a write recovery time of a memory device. In an embodiment, thermal detection logic detects a signal from a thermal...
US-9,390,784 Semiconductor memory device and semiconductor package
A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including...
US-9,390,783 Memory devices and systems including cache devices for memory modules
A memory apparatus may include one or more cache memory integrated circuit (ICs), each of which may have compare circuitry that compares a received address with...
US-9,390,782 Memory with refresh logic to accommodate low-retention storage rows
An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes...
US-9,390,781 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first...
US-9,390,780 Semiconductor memory device
A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal...
US-9,390,779 System and method of sensing a memory cell
A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance...
US-9,390,778 Semiconductor memory devices and memory systems including the same
A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows...
US-9,390,777 Memory controller for strobe-based memory systems
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe...
US-9,390,776 Data strobing circuit and semiconductor apparatus using the same
A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock...
US-9,390,775 Reference voltage setting circuit and method for data channel in memory system
A semiconductor memory system includes a memory controller and memory apparatus. The memory controller provides a first data having a first level and a second...
US-9,390,774 Systems and methods of storing data
A method includes, when using a binary cache in an multi-level cell (MLC) flash memory splitting a codeword corresponding to a data page into multiple data...
US-9,390,773 Shiftable memory
A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a...
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