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Patent # Description
US-9,390,018 Data cache prefetch hints
The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher...
US-9,390,017 Write and read collision avoidance in single port memory devices
A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write...
US-9,390,016 Accessing an off-chip cache via silicon photonic waveguides
The disclosed embodiments provide a system in which a processor chip accesses an off-chip cache via silicon photonic waveguides. The system includes a processor...
US-9,390,015 Method for performing cacheline polling utilizing a store and reserve instruction
A method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance...
US-9,390,014 Synchronizing updates of page table status indicators and performing bulk operations
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page...
US-9,390,013 Coherent attached processor proxy supporting coherence state update in presence of dispatched master
A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent...
US-9,390,012 Multi-core processor system, cache coherency control method, and computer product
A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple...
US-9,390,011 Zero cycle clock invalidate operation
A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU...
US-9,390,010 Cache management
The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the...
US-9,390,009 Configuration mapping using a multi-dimensional rule space and rule consolidation
A configuration mapping system and method increase the effectiveness of mapping of information from an established product line to a new product offering. In at...
US-9,390,008 Data encoding for non-volatile memory
A data storage device includes a memory device and a controller. Mapping circuitry is configured, in response to receiving data, to apply a one-to-many mapping...
US-9,390,007 Method and apparatus for performing adaptive memory bank addressing
A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and...
US-9,390,006 Garbage collection of an object
One or more embodiments are directed to creating a structure comprising a weak reference to an object, a strong reference to the object, a count of remote...
US-9,390,005 Method for reading a data block of a nonvolatile memory of a control unit
A method for reading a data block of a nonvolatile memory of a processing unit, the nonvolatile memory being subdivided into sectors; the sectors being written...
US-9,390,004 Hybrid memory management
Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be...
US-9,390,003 Retirement of physical memory based on dwell time
In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of regions of physical memory. The data storage...
US-9,390,002 Efficient bin labeling schemes for tracking cells in solid state storage devices
Information associated with a read to solid state storage is received, including a read number and a read value. The read value is written to a location in a...
US-9,390,001 Nonvolatle memory device and memory system having the same, and related memory management, erase and...
An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation...
US-9,390,000 Memory system in which data is written to memory chips based on a distance from a memory controller
A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The...
US-9,389,999 System and method for emulating an EEPROM in a non-volatile memory device
The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in...
US-9,389,998 Memory formatting method, memory controller, and memory storage apparatus
A memory formatting method adapted to a memory storage apparatus is provided. The memory formatting method includes configuring a plurality of logical block...
US-9,389,997 Heap management using dynamic memory allocation
Embodiments of the present invention provide a method, system, and program product for heap management using dynamic memory allocation. The method comprises...
US-9,389,996 Field apparatus
A field apparatus includes a first memory that stores a program specifying an operation of the field apparatus; a second memory that stores parameters to be...
US-9,389,995 Optimization of Map-Reduce shuffle performance through snuffler I/O pipeline actions and planning
A shuffler receives information associated with partition segments of map task outputs and a pipeline policy for a job running on a computing device. The...
US-9,389,994 Optimization of map-reduce shuffle performance through shuffler I/O pipeline actions and planning
A shuffler receives information associated with partition segments of map task outputs and a pipeline policy for a job running on a computing device. The...
US-9,389,993 System and method for whitelist management
A method is provided in one embodiment and includes receiving a request for a session at a network element; communicating a query for whitelist data to a...
US-9,389,992 Multiple tracer configurations applied on a function-by-function level
A tracing system may use different configurations for tracing various functions in different manners. A configuration may be a group of settings that may define...
US-9,389,991 Methods, systems, and computer readable mediums for generating instruction data to update components in a...
Methods, systems, and computer readable mediums for generating instruction data to update components in a converged infrastructure system are disclosed....
US-9,389,990 Self verifying device driver for multi-version compatible data manipulation devices
A method, system, and computer program product are described. The system includes a first memory device to store programming code of the device driver, the...
US-9,389,989 Self verifying device driver for multi-version compatible data manipulation devices
A method, system, and computer program product are described. The method of testing a device driver includes executing a test case for the device driver, the...
US-9,389,988 Method and system for authorization based routing of failed test scenarios
Automatic authorization-based routing of failed test scenarios, including: receiving descriptions of test scenarios that failed while executed by an automatic...
US-9,389,987 Method and system for identifying missing test scenarios by comparing authorized processes with available test...
Identifying missing test scenarios based on authorization policies, including: analyzing the authorization policies applied to non-super-users of a specific...
US-9,389,986 Identifying impacted tests from statically collected data
The present invention extends to methods, systems, and computer program products for identifying impacted tests from statically collected data. In general,...
US-9,389,985 Codepath integrity checking
A method and apparatus for testing code is provided. The method includes inserting at least one token in program code, wherein each token comprises a code...
US-9,389,984 Directing verification towards bug-prone portions
A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify...
US-9,389,983 Verification of complex systems that can be described by a finite state transition system
A method including the steps of: generating a system model, the model comprising an initial state, a transition between consecutive states and a property...
US-9,389,982 Method and apparatus for monitoring an in-memory computer system
An in-memory computing system for conducting on-line transaction processing and on-line analytical processing includes system tables in main memory to store...
US-9,389,981 Hierarchical live graphs for performance data display
A system performance analysis user interface includes a thumbnail portion and an analysis view portion. One or more performance indicator thumbnails and/or data...
US-9,389,980 Detecting events in cloud computing environments and performing actions upon occurrence of the events
A monitoring system can monitor computing processes in clouds. The monitoring system can monitor the clouds for certain events associated with the computing...
US-9,389,979 Debug system, and related integrated circuit and method
A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective...
US-9,389,978 Automated operating system test framework
Techniques for automating testing of a first computing system comprises identifying a plurality of system interface elements of a second computing system;...
US-9,389,977 Fault injection testing apparatus and method
Provided are fault injection testing apparatus and method which inject faults that may occur in a system or a source file that a user wants to examine and...
US-9,389,976 Distributed persistent memory using asynchronous streaming of log records
Technologies for distributed durable data replication include a computing device having persistent memory that stores a memory state and an update log. The...
US-9,389,975 Method and apparatus to utilize large capacity disk drives
A method of utilizing storage in a storage system comprises prioritizing a plurality of storage areas in the storage system for data recovery with different...
US-9,389,974 Data retrieval from stacked computer memory
Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The...
US-9,389,973 Memory error propagation for faster error recovery
A method for managing a corrupted memory block. The method includes detecting the corrupted memory block, and removing, after detecting the corrupted memory...
US-9,389,972 Data retrieval from stacked computer memory
Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The...
US-9,389,971 Redundant automation system and method for operating the redundant automation system
A redundant automation system and a method for operating the redundant automation system which is provided with a first subsystem and a second subsystem that...
US-9,389,970 Selected virtual machine replication and virtual machine restart techniques
Methods, systems, and articles of manufacture for selected VM replication and VM restart techniques are provided herein. A method includes selecting a sub-set...
US-9,389,969 Method for SIP proxy failover
For SIP proxy failover in a SIP telecommunication network (SIPN) comprising a plurality of proxies (P1, P2) and a domain name server (DNSR), the method...
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