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Patent # Description
US-9,397,682 Reference buffer with wide trim range
Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an...
US-9,397,681 Analog/digital converter system and associated method for checking a multiplexer for an analog/digital converter
An analog/digital converter system includes a multiplexer, which includes multiple channels having at least one switch, and an analog/digital converter, the...
US-9,397,680 Receiver with adjustable reference voltages
A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver...
US-9,397,679 Circuit and method for DAC mismatch error detection and correction in an ADC
A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an...
US-9,397,678 Localized dynamic element matching and dynamic noise scaling in digital-to-analog converters (DACs)
Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In...
US-9,397,677 Method and system for digital-to-analog converter performance measurement using equivalent-time sampler
A system and method: provide a digital input signal to a digital-to-analog converter (DAC) which, in response to a DAC clock signal, converts the digital input...
US-9,397,676 Low power switching techniques for digital-to-analog converters
Embodiments of the present disclosure provide improved switching techniques for controlling three-level DAC cells employing a return-to-hold scheme. Disclosed...
US-9,397,675 Hybrid frequency synthesizer and method
Embodiments include a hybrid frequency synthesizer comprising a direct digital synthesizer configured to generate a digital output signal having a frequency...
US-9,397,674 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and...
A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output...
US-9,397,673 Oscillator crosstalk compensation
Systems and methods for mitigating crosstalk between controlled oscillators of Phase-Locked Loops (PLLs) are disclosed. In one embodiment, a system includes a...
US-9,397,672 Semiconductor device
A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of...
US-9,397,671 Delay locked loop and semiconductor apparatus
A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop...
US-9,397,670 Edge generator-based phase locked loop reference clock generator for automated test system
An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge...
US-9,397,669 System and method for process and temperature calibration of capacitor-based oscillators
A method and device for calibrating an oscillator and a temperature sensor in an electronic device are provided. A same temperature cycle, which includes at...
US-9,397,668 System and method for providing programmable synchronous output delay in a clock generation or distribution device
A clock frequency division circuit receives delay value, synchronization signal, and external clock signal of a given frequency. The clock division circuit...
US-9,397,667 Shared divide by N clock divider
A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division...
US-9,397,666 Fault protection for clock tree circuitry
An Integrated Circuit (IC) includes clock-tree circuitry and protection circuitry. The clock-tree circuitry is configured to distribute a clock signal across...
US-9,397,665 Programmable structured arrays
A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited...
US-9,397,664 Programmable logic circuit
A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of...
US-9,397,663 Fault protection for high-fanout signal distribution circuitry
An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a...
US-9,397,662 Sequential circuit with current mode error detection
A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of...
US-9,397,661 On-die termination circuit and on-die termination method
An ODT circuit capable of generating an OCD/ODT code and/or a reference voltage adaptively adjusted according to a system environment is disclosed. The ODT...
US-9,397,660 Touch panel
A touch panel including a substrate, first electrodes, second electrodes, first wires, second wires and a means for shortening a gap between the second...
US-9,397,659 Touch screen panel for display device and method of manufacturing the same
A touch screen panel for a display device includes layers of polymer formed on both sides of a substrate for forming driving electrodes and sensing electrodes....
US-9,397,658 Gate drive circuit and a method for controlling a power transistor
A gate drive circuit drives a control terminal of a power transistor and comprises: a drive terminal for electrically coupling the control terminal, a first...
US-9,397,657 Methods and systems for operating hybrid power devices using multiple current-dependent switching patterns
An integrated circuit includes a hybrid switch having first and second switching devices of different type therein. A control circuit is provided, which is...
US-9,397,656 Circuit and method for controlling charge injection in radio frequency switches
A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a ...
US-9,397,655 Discharge circuit for power supply unit
A discharge circuit includes a pulse width modulator (PWM) chip, a first and second electronic switch, and a resistor. The first electronic switch receives a...
US-9,397,654 Low power externally biased power-on-reset circuit
Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting...
US-9,397,653 Semiconductor device
According to one embodiment, the semiconductor device includes a power-on reset circuit and a constant voltage generation circuit. The power-on reset circuit...
US-9,397,652 Circuitry and method for operating such circuitry
A circuitry is suggested, in particular a power switch, comprising a first electronic switch with an isolated gate; a second electronic switch with an isolated...
US-9,397,651 Dynamically driven deep n-well circuit
A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node,...
US-9,397,650 Gate driving apparatus
A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive...
US-9,397,649 Semiconductor device and display device
A semiconductor device is provided with an oxide semiconductor thin-film transistor (TFT); a calibration electrode that is positioned so as to face an oxide...
US-9,397,648 Systems, circuitry, and methods for decoding pulse width modulated signal
A first charge module includes a first resistor and a first capacitor. A second charge module includes a second resistor and a second capacitor. A voltage...
US-9,397,647 Clock spurs reduction technique
Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled...
US-9,397,646 Delay circuit
Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay...
US-9,397,645 Circuit for common mode removal for DC-coupled front-end circuits
In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first...
US-9,397,644 Frequency doubler
A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different...
US-9,397,643 Linear triangular wave generator with stray effect compensation and associated method for compensating stray effect
A linear triangular wave generator with stray effect compensation includes a linear triangular wave generating module, a negative impedance converting module,...
US-9,397,642 Latch circuit
A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable...
US-9,397,641 Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first...
US-9,397,640 Latch circuit and semiconductor device including the same
A latch circuit includes: first to Nth storage nodes where N is an even number equal to or more than four; and first to Nth pairs of transistors, each of which...
US-9,397,639 Integrated circuitry for generating a clock signal in an implantable medical device
Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer...
US-9,397,638 Implementing adaptive control for optimization of pulsed resonant drivers
A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject...
US-9,397,637 Voltage controlled oscillator, semiconductor device, and electronic device
A low-power voltage controlled oscillator is provided. The voltage controlled oscillator includes (2n+1) first circuit components (n is an integer of one or...
US-9,397,636 System and method for driving transistors
In accordance with an embodiment, a circuit includes a first transistor, a second transistor having a reference node coupled to an output node of the first...
US-9,397,635 Segmented attenuator with glitch reduction
A method and circuit for significantly reducing the switching transients of a digital step attenuator (DSA) by employing a segmented architecture that combines...
US-9,397,634 Filter, duplexer and communication module
In a filter, two parallel resonators that are adjacent to each other are connected, in parallel, to a first portion of the signal line that connects a pair of...
US-9,397,633 Acoustic wave device
A SAW device (1) comprises a substrate (3); SAW elements (10) on a first main surface (3a) of the substrate (3); first lines (intermediate lines (29) and output...
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