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Patent # Description
US-9,397,230 Zener diode devices and related fabrication methods
Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener...
US-9,397,229 Nano resonance apparatus and method
A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode...
US-9,397,228 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes...
US-9,397,227 Split gate flash cell semiconductor device
A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor...
US-9,397,226 Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts
An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a...
US-9,397,225 Semiconductor device and method for manufacturing the same
In the transistor including an oxide semiconductor film, which includes a film for capturing hydrogen from the oxide semiconductor film (a hydrogen capture...
US-9,397,224 Semiconductor device
A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by...
US-9,397,223 Oxide thin film transistor with a metal oxide etch barrier layer, method of manufacturing the same and display...
Embodiments of the invention provide a thin film transistor, a method of manufacturing the same, an array substrate comprising the thin film transistor and a...
US-9,397,222 Display device and electronic device
An object is, in a structure where switch circuits in a signal line driver circuit is placed over the same substrate as a pixel portion, to reduce the size of...
US-9,397,221 Thin film transistor, manufacturing method thereof and thin film transistor array substrate
The present invention discloses a thin film transistor, comprising an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain...
US-9,397,220 Thin film transistor
A thin film transistor disposed on a substrate is provided. The thin film transistor includes a channel, a gate, a source, a drain and an etching stop layer....
US-9,397,219 Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such...
Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of...
US-9,397,218 Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices
Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is...
US-9,397,217 Contact structure of non-planar semiconductor device
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a...
US-9,397,216 Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast...
US-9,397,215 FinFET with reduced source and drain resistance
A method for forming a semiconductor device comprises patterning and etching a fin in a semiconductor substrate, forming a gate stack over the fin, epitaxially...
US-9,397,214 Semiconductor device
A semiconductor device is provided includes a substrate, a gate structure formed on the substrate, an epitaxial source/drain structure respectively formed at...
US-9,397,213 Trench gate FET with self-aligned source contact
A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and...
US-9,397,212 Power converter package including top-drain configured power FET
In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a...
US-9,397,211 Lateral MOSFET with buried drain extension layer
An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the...
US-9,397,210 Forming air gaps in memory arrays and memory arrays with air gaps thus formed
A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an...
US-9,397,209 Semiconductor structure and manufacturing method of forming a large pattern and a plurality of fine gate lines...
A semiconductor structure has a second portion with an appendage on one side of the second portion and extruding along the longitudinal direction of the second...
US-9,397,208 Compound semiconductor device
A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor...
US-9,397,207 Gated thyristor power device
An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the...
US-9,397,206 Semiconductor device and method for manufacturing the same
A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. In the semiconductor device, the...
US-9,397,205 Semiconductor device
A semiconductor device includes a substrate, a first doped well disposed in the substrate, a second doped well disposed in the substrate adjacent to a first...
US-9,397,204 Heterojunction bipolar transistor with two base layers
A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first...
US-9,397,203 Lateral silicon-on-insulator bipolar junction transistor process and structure
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed...
US-9,397,202 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a...
US-9,397,201 Non-volatile memory (NVM) cell and a method of making
A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the...
US-9,397,200 Methods of forming 3D devices with dielectric isolation and a strained channel region
One illustrative method involves forming a FinFET device or a nanowire device by forming a sacrificial gate structure above a substantially vertically oriented...
US-9,397,199 Methods of forming multi-Vt III-V TFET devices
The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a...
US-9,397,198 Method of manufacturing semiconductor device having fin gate
A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active...
US-9,397,197 Forming wrap-around silicide contact on finFET
A technique relates to a transistor. Dummy gates are formed on top of an isolation layer and over fins. Pillars are along sides of fins such that trenches...
US-9,397,196 Methods of manufacturing semiconductor devices that include performing hydrogen plasma treatment on insulating...
In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate...
US-9,397,195 Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates
Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of...
US-9,397,194 Method for manufacturing semiconductor device with oxide semiconductor ohmic conatct layers
A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide...
US-9,397,193 Semiconductor integrated circuit apparatus and method of manufacturing the same
A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a...
US-9,397,192 Semiconductor integrated circuit apparatus and method of manufacturing the same
A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a...
US-9,397,191 Methods of making a self-aligned channel drift device
An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent...
US-9,397,190 Fabrication method of semiconductor structure
A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material...
US-9,397,189 Semiconductor structure having a metal gate with side wall spacers
A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is...
US-9,397,188 Group III-N nanowire transistors
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a...
US-9,397,187 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,397,186 Method of fabricating a gallium nitride merged P-I-N schottky (MPS) diode by regrowth and etch back
An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second...
US-9,397,185 Semiconductor device
A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the...
US-9,397,184 Semiconductor device having metal gate and manufacturing method thereof
A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial...
US-9,397,183 Semiconductor memory device with ONO stack
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first...
US-9,397,182 Transistor structure with silicided source and drain extensions and process for fabrication
A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel...
US-9,397,181 Diffusion-controlled oxygen depletion of semiconductor contact interface
A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the...
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