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Patent # Description
US-9,397,180 Low resistance sinker contact
An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into...
US-9,397,179 Semiconductor device
A semiconductor device including an active region having a field insulating layer disposed at a first side thereof; a first wire pattern formed on the active...
US-9,397,178 Split gate power semiconductor field effect transistor
The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power...
US-9,397,177 Variable length multi-channel replacement metal gate including silicon hard mask
A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor...
US-9,397,176 Method of forming split gate memory with improved reliability
A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second...
US-9,397,175 Multi-composition gate dielectric field effect transistors
A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate...
US-9,397,174 Self-aligned gate electrode diffusion barriers
A structure that provides a diffusion barrier between two doped regions. The structure includes a diffusion barrier including a semiconductor layer comprising a...
US-9,397,173 Wide bandgap transistor devices with field plates
A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate...
US-9,397,172 Semiconductor epitaxial wafer
Provided is a semiconductor epitaxial wafer with reduced metal contamination achieved by higher gettering capability. The semiconductor epitaxial wafer includes...
US-9,397,171 Semiconductor device and manufacturing method for the same
A semiconductor device according to the invention includes an epitaxial layer of a first conductivity type, a first well of a second conductivity type to which...
US-9,397,170 Ga2O3 semiconductor element
A Ga.sub.2O.sub.3 semiconductor element includes: an n-type .beta.-Ga.sub.2O.sub.3 single crystal film, which is formed on a high-resistance...
US-9,397,169 Epitaxial structures
An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a...
US-9,397,168 Method to define the active region of a transistor employing a group III-V semiconductor material
A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged...
US-9,397,167 Nitride semiconductor wafer, nitride semiconductor device, and method for manufacturing nitride semiconductor wafer
A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate...
US-9,397,166 Strained channel region transistors employing source and drain stressors and systems including the same
Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source...
US-9,397,165 Active regions with compatible dielectric layers
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure...
US-9,397,164 Deep collector vertical bipolar transistor with enhanced gain
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base...
US-9,397,163 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-9,397,162 FinFET conformal junction and abrupt junction with reduced damage method and device
A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a...
US-9,397,161 Reduced current leakage semiconductor device
A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed...
US-9,397,160 Semiconductor device
Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have...
US-9,397,159 Silicide region of gate-all-around transistor
The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from...
US-9,397,158 Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion
A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to...
US-9,397,157 Multi-gate device structure including a fin-embedded isolation region and methods thereof
A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and...
US-9,397,156 Semiconductor device and method of manufacturing the same
To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy...
US-9,397,155 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes a silicon carbide layer, an element region including a semiconductor element portion formed in the silicon...
US-9,397,154 Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
This invention discloses a semiconductor power device formed in a semiconductor substrate of a first conductivity type comprises an active cell area and a...
US-9,397,153 Semiconductor device
Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can...
US-9,397,152 Multilayer MIM capacitor
A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by...
US-9,397,151 Packaged integrated circuits having high-Q inductors therein and methods of forming same
A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess...
US-9,397,150 Top emission type organic light emitting display device and method of manufacturing the same
A top-emission type light emitting display device and a corresponding manufacturing method are described. A device substrate has display area and non-display...
US-9,397,149 Semiconductor device
A display device that includes a first flexible substrate, a first bonding layer over the first flexible substrate, a first insulating film over the first...
US-9,397,148 Organic electroluminescence display device
Provided is an organic electroluminescence display device. The organic electroluminescence display device includes a bank that is provided so as to surround a...
US-9,397,147 Self-light emitting display unit and electronic device
A self-light emitting display unit capable of improving manufacturing yield is provided. Sizes of color pixel circuits corresponding to pixels for R, G, and B...
US-9,397,146 Vertical random access memory with selectors
Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical...
US-9,397,145 Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory...
A memory structure comprises first conductive lines extending in a first direction over portions of a base structure, storage element structures extending in...
US-9,397,144 Non-volatile semiconductor memory device
According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second...
US-9,397,143 Liner for phase change memory (PCM) array and associated techniques and configurations
Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a...
US-9,397,142 Semiconductor device and method for producing semiconductor device
A semiconductor device includes a pillar-shaped resistance-changing layer on a contact and a reset gate insulating film that surrounds the pillar-shaped...
US-9,397,141 Current selector for non-volatile memory in a cross bar array based on defect and band engineering...
Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non...
US-9,397,140 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a stack of films including a conductive film layer above a semiconductor substrate; patterning...
US-9,397,139 Integrated inductor and magnetic random access memory device
Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first upper...
US-9,397,138 Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to...
US-9,397,137 Interconnect structure for CIS flip-chip bonding and methods for forming the same
A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and...
US-9,397,136 Solid-state imaging device, method for manufacturing solid-state imaging device, and imaging apparatus
A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically...
US-9,397,135 Active pixel sensor having a raised source/drain
An integrated circuit having an array of APS cells. Each cell in the array has at least one transistor source or drain region that is raised relative to a...
US-9,397,134 Methods and devices configured to provide selective heat transfer of an integrated circuit
Methods and devices configured to provide selective heat transfer of a temperature-sensitive circuit are provided. In an example, a device comprises a thinned...
US-9,397,133 Solid-state image sensor and electronic device
There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the...
US-9,397,132 Solid-state imaging device, members for the same, and imaging system
The present invention provides a solid-state imaging device including a pad capable of reducing inferior connection with an external terminal. The solid-state...
US-9,397,131 Solid-state imaging apparatus having electrical connection portions with lengths extending in first direction...
The present invention relates to a solid-state imaging apparatus including a first substrate having a plurality of photoelectric conversion units and a second...
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