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Patent # Description
US-9,397,130 CMOS image sensor structure with crosstalk improvement
A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The...
US-9,397,129 Dielectric film for image sensor
Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array...
US-9,397,128 Process for forming a stack of different materials, and device comprising this stack
A stack of layers defines a filter and is formed by copper on hydrogenated silicon nitride supported by a carrier. The filter includes a layer of hydrogenated...
US-9,397,127 Thin film transistor array panel and method of manufacturing the same
An exemplary embodiment provides a thin film transistor array panel including: a substrate; a gate line; a semiconductor layer; a data wire layer; a first...
US-9,397,126 Peeling apparatus and manufacturing apparatus of semiconductor device
To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the...
US-9,397,125 Pixel unit and method of manufacturing the same, array substrate and display device
Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are...
US-9,397,124 Organic light-emitting diode display with double gate transistors
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode and thin-film transistor circuitry that...
US-9,397,123 Array substrate, manufacture method thereof, and display device
An array substrate is disclosed. The Array substrate includes gate and data lines, where the gate lines and the data lines cross each other. The pixel units...
US-9,397,122 Organic lighting emitting display device including light absorbing layer and method for manufacturing same
Provided is a display device including: a plurality of pixels where a plurality of gate lines cross a plurality of data lines, respectively, each of the pixels...
US-9,397,121 Array substrate and method for manufacturing the same, display device
The present disclosure provides an array substrate including a substrate, a plurality of pixel units arranged on the substrate. Each pixel unit includes a TFT,...
US-9,397,120 Array substrate and a display device having the same
An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first...
US-9,397,118 Thin-film ambipolar logic
An ambipolar electronic device is disclosed. The device may include a field-effect transistor (FET), which may have a handle substrate layer, two contacts and...
US-9,397,117 Display device
The display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting...
US-9,397,116 Semiconductor device having a closed cavity structure and method of manufacturing the same
A semiconductor device may include a first dielectric layer. The semiconductor device may further include a second dielectric layer overlapping the first...
US-9,397,115 Methods for making a trim-rate tolerant self-aligned contact via structure array
A stack is formed over a substrate, which comprises an alternating plurality of first material layers including a first material and second material layers...
US-9,397,114 Methods of fabricating three-dimensional semiconductor memory devices
Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers...
US-9,397,113 Memory architecture of array with single gate memory devices
A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged...
US-9,397,112 L-shaped capacitor in thin film storage technology
The present disclosure relates to a non-planar FEOL (front-end-of-the-line) capacitor comprising a charge trapping dielectric layer disposed between electrodes,...
US-9,397,111 Select gate transistor with single crystal silicon for three-dimensional memory
A fabrication process for a 3D memory structure provides a single crystal silicon channel for a drain-side select gate (SGD) transistor using a laser thermal...
US-9,397,110 3D independent double gate flash memory
A memory device configurable for independent double gate cells, storing multiple bits per cell includes multilayer stacks of conductive strips configured as...
US-9,397,109 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion,...
US-9,397,108 3-D non-volatile memory device and method of manufacturing the same
A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a...
US-9,397,107 Methods of making three dimensional NAND devices
A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate....
US-9,397,106 Method for producing MROM memory based on OTP memory
A method of producing a Macro Read Only Memory (MROM) memory based on a One Time Programmable (OTP) memory is provided. The method includes: removing a floating...
US-9,397,105 Nanodot charge storage structures
Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of...
US-9,397,104 SRAM cell and method for manufacturing the same
In one embodiment, a SRAM cell may include a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first...
US-9,397,103 Dynamic memory structure
A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and...
US-9,397,102 III-V layers for N-type and P-type MOS source-drain contacts
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example...
US-9,397,101 Stacked common gate finFET devices for area optimization
A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor...
US-9,397,100 Hybrid high-k first and high-k last replacement gate process
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric...
US-9,397,099 Semiconductor device having a plurality of fins and method for fabricating the same
A semiconductor device having a plurality of fins including at least one first fin and at least one second fin formed on a semiconductor substrate is provided....
US-9,397,098 FinFET-based ESD devices and methods for forming the same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is...
US-9,397,097 Gate structure for semiconductor device
A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral...
US-9,397,096 Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same, wherein an example method may include: forming a first semiconductor layer and a second...
US-9,397,095 Power and die size optimization in FinFETs
A FinFET comprises a substrate, an array of substantially parallel fins formed on the substrate and extending in a first direction, and an array of gates on the...
US-9,397,094 Semiconductor structure with an L-shaped bottom plate
A semiconductor structure having a first source/drain semiconductor structure connected to a vertical channel such that the source/drain semiconductor structure...
US-9,397,093 Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof
A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material, etching...
US-9,397,092 Semiconductor device in a semiconductor substrate and method of manufacturing a semiconductor device in a...
A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench...
US-9,397,091 Semiconductor component arrangement comprising a trench transistor
A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body...
US-9,397,090 Semiconductor device
A semiconductor device includes first metal-on-semiconductor (MOS), second MOS, and bipolar junction (BJ) structures formed in a substrate. The first MOS...
US-9,397,089 Group III-V HEMT having a selectably floating substrate
There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a...
US-9,397,088 Semiconductor device
In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and...
US-9,397,087 Distributed electrostatic discharge protection circuit with magnetically coupled differential inputs and outputs
A distributed electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection elements and a current balancing network...
US-9,397,086 Passive devices for FinFET integrated circuit technologies
Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type...
US-9,397,085 Bi-directional ESD protection device
An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is...
US-9,397,084 Structure of ESD protection circuits on BEOL layer
A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed...
US-9,397,083 Semiconductor device including protruding power supply wirings with bent portions at ends thereof
There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout...
US-9,397,082 Multiple die lead frame packaging
First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each...
US-9,397,081 Fabrication method of semiconductor package having embedded semiconductor elements
A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the...
US-9,397,080 Package on package devices and methods of packaging semiconductor dies
A method of packaging semiconductor dies may include: coupling a first die to a first substrate; forming a plurality of first portions of a plurality of metal...
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