At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Multichip integration with through silicon via (TSV) die embedded in
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as...
Semiconductor device assembly with underfill containment cavity
Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first...
Display device having film substrate
A display device comprises: a film substrate; display pixels; a flexible printed circuit board and/or a driver integrated circuit; a protective resin that...
Optoelectronic semiconductor apparatus and carrier assembly
A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with...
Illuminated glass panel for a vehicle, and manufacture thereof
An illuminating glazing unit for a vehicle includes a first sheet made of mineral or organic glass, a peripheral light source with a support profiled member...
Semiconductor device package and method of manufacturing the same
A semiconductor package includes a substrate, a set of electrical components, a stud, a tapering electrical interconnection and a package body. The electrical...
Method of using a back-end-of-line connection structure to distribute
current envenly among multiple TSVs in a...
A method of using a BEOL connection structure to distribute current evenly among multiple TSVs in a series for delivery to a top die and a BS-RDL PDN to...
Method of manufacturing semiconductor device
Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is...
High density interconnection of microelectronic devices
A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically...
Method for forming package structure
A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes...
Semiconductor device and method of adaptive patterning for panelized
packaging with dynamic via clipping
A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating...
Package in package (PiP) electronic device and manufacturing method
A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface...
A bonding device includes a first feeding mechanism, a second feeding mechanism, a glue spraying mechanism positioned between the first feeding mechanism and...
Bond wire feed system and method therefor
A bond wire feed system has a wire tensioning unit with a chamber that has a wire inlet aperture and a wire outlet aperture. The wire inlet and outlet apertures...
Fixture design for pre-attachment package on package component assembly
Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a...
Aluminum alloy wire for bonding applications
The invention is related to a bonding wire containing a core having a surface. The core contains aluminum as a main component and scandium in an amount between...
Microelectronic packages with nanoparticle joining
A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first...
Package on package bonding structure and method for forming the same
The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of...
A semiconductor device includes a wiring layer formed on a first surface of a first insulation layer and including an external connection pad and an internal...
Package on package structure
A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the...
Bonded structures for package and substrate
The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially...
Semiconductor device and method of forming patterned repassivation
openings between RDL and UBM to reduce...
A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is...
Plurality of semiconductor devices in resin with a via
According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive...
Semiconductor device having trench adjacent to receiving area and method
of forming the same
In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure...
Processing of thick metal pads
In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region...
Semiconductor structure with an interconnect level having a conductive pad
and metallic structure such as a...
A semiconductor structure with an interconnect level above a substrate and including a conductive pad and a metallic structure, such as a base of a crackstop. A...
Molded device with anti-delamination structure providing multi-layered
The present invention provides a molded encapsulated multi-layered semiconductor device, comprising a first substrate, a second substrate and an...
A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the...
Warpage reduction in structures with electrical circuitry
To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing...
Semiconductor device and method of forming pre-molded semiconductor die
having bumps embedded in encapsulant
A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected...
Gate tie-down enablement with inner spacer
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a first through hole disposed in the substrate and filled with conductive material, and a second through hole...
Interconnect structure and method of forming the same
A structure includes a first metal line and a second metal line disposed on a first side of a substrate, and a dielectric structure separating the first metal...
Fluorine-free word lines for three-dimensional memory devices
Fluorine-induced formation of voids and electrical shorts can be avoided by forming fluorine-free metal lines. Specifically, control gate electrodes of a...
Structure and formation method of damascene structure
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive...
Semiconductor device and method for forming the same
A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and...
Semiconductor memory device
A semiconductor memory device according to an embodiment comprises a stacked body, the stacked body including a plurality of conductive layers disposed on a...
Integrated helical multi-layer inductor structures
A chip package comprising: a chip stack comprising at least one chip; and a thermal power plane comprising at least two substantially parallel dielectric layers...
Semiconductor device comprising metal plug having substantially convex
A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug...
Semiconductor device and method for forming the same
A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and...
Microelectronic components with features wrapping around protrusions of
conductive vias protruding from...
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A,...
A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat...
Semiconductor package assembly
Embodiments of the present disclosure provide an apparatus comprising a substrate having (i) a first side configured to receive a semiconductor die and (ii) a...
Integrated ingot for TSV substrates and method for making the same
The disclosure describes a metal-wire-based method for making an integrated ingot, which basically comprises a dielectric matrix and a patterned array of metal...
Multi-chip package having a stacked plurality of different sized
semiconductor chips, and method of...
Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate,...
The semiconductor device in accordance with one mode comprises a semiconductor chip; a chip mounting substrate on which the semiconductor chip is mounted; a...
Guard ring structure and method for forming the same
A guard ring structure is provided, including a semiconductor substrate with a circuit region encircled by a first ring and a second ring. In one embodiment,...
Post-mold for semiconductor package having exposed traces
Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor...
A semiconductor module is provided for shortening a manufacturing tact time, reducing manufacturing costs and for ensuring reliability of a bonding portion. The...
Power semiconductor package device having locking mechanism, and
preparation method thereof
A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin,...