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Patent # Description
US-9,397,028 Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed.
US-9,397,027 Sacrificial pad on semiconductor package device and method
A semiconductor package device, electronic device, and fabrication methods are described that include at least one sacrificial contact pad as a portion of the...
US-9,397,026 Semiconductor device having flat leads
A semiconductor device comprises a semiconductor chip mounted on an island, and a plurality of leads spaced form the island and connected by wires to the...
US-9,397,025 Semiconductor device and method for manufacturing thereof
The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper...
US-9,397,024 Semiconductor devices with optical through via structures, memory cards including the same, and electronic...
A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate. The through via...
US-9,397,023 Integration of heat spreader for beol thermal management
A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader...
US-9,397,022 Semiconductor device having a locally reinforced metallization structure
A semiconductor device includes a semiconductor substrate having a first side, at least a first area formed in the semiconductor substrate, at least a second...
US-9,397,021 Electrical connector
An electrical connector for electrically connecting a chip module to a circuit board, includes an insulating body, multiple conducting bodies, and multiple...
US-9,397,020 Semiconductor package
A semiconductor package includes a substrate including a lower plate and an upper plate, a semiconductor chip mounted on a top surface of the substrate, and a...
US-9,397,019 Integrated circuit package configurations to reduce stiffness
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed...
US-9,397,018 Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for...
A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation...
US-9,397,017 Substrate structures and methods of manufacture
A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of...
US-9,397,016 Flip chip assembly process for ultra thin substrate and package on package assembly
In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless...
US-9,397,015 Semiconductor device and semiconductor device casing
A semiconductor device has an insulating substrate, a semiconductor element which is mounted on the insulating substrate, a hollow casing which surrounds a...
US-9,397,014 Semiconductor device having laterally-extending electrode with reduced inductance
An electrode includes an extending portion extending such that both ends thereof get into a first recessed portion and a second recessed portion provided in a...
US-9,397,013 Method of controlling an etching process for forming fine patterns of a semiconductor device
A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings...
US-9,397,012 Test pattern for feature cross-sectioning
A method includes forming a first plurality of instances of a first pattern on a substrate. The first pattern includes a plurality of features defining a first...
US-9,397,011 Systems and methods for reducing copper contamination due to substrate processing chambers with components made...
Systems and methods for reducing copper contamination in a substrate processing system include performing a plasma process on a substrate in a processing...
US-9,397,010 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench;...
US-9,397,009 Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer...
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the...
US-9,397,008 Semiconductor device and manufacturing method of conductive structure in semiconductor device
A manufacturing method of a conductive structure in a semiconductor device includes the following steps. A plurality of gate structures are formed on a...
US-9,397,007 Method for manufacturing semiconductor structure through forming an additional layer inside opening of a...
The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a...
US-9,397,006 Co-integration of different fin pitches for logic and analog devices
A method includes forming a first set of fins on a substrate; forming a second set of fins on the substrate; forming a gate stack over the fins and substrate;...
US-9,397,005 Dual-material mandrel for epitaxial crystal growth on silicon
In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a...
US-9,397,004 Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings
A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal...
US-9,397,003 Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques
A method includes forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised...
US-9,397,002 Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide
A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin...
US-9,397,001 Method for manufacturing electronic device comprising a resin substrate and an electronic component
An electronic component manufacturing method according to an aspect of the present disclosure includes providing a support substrate, forming a release layer...
US-9,397,000 Wafer processing method
A wafer has a substrate and a laminated layer formed on the substrate. The laminated layer includes low-permittivity insulating films. The laminated layer forms...
US-9,396,999 Wafer level packaging method
A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure....
US-9,396,998 Semiconductor device having fan-in and fan-out redistribution layers
According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected...
US-9,396,997 Method for producing a semiconductor component with insulated semiconductor mesas
A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface...
US-9,396,996 Methods of forming openings in semiconductor structures
A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of...
US-9,396,995 MOL contact metallization scheme for improved yield and device reliability
A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON...
US-9,396,994 Semiconductor device and method for manufacturing the same
The present invention relates to a semiconductor device and a method for manufacturing the same. Disclosed is a semiconductor device including a substrate, a...
US-9,396,993 Device having reduced pad peeling during tensile stress testing and a method of forming thereof
The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming...
US-9,396,992 Method of using a barrier-seed tool for forming fine-pitched metal interconnects
A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the...
US-9,396,991 Multilayered contact structure having nickel, copper, and nickel-iron layers
A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by...
US-9,396,990 Capping layer for improved deposition selectivity
The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme...
US-9,396,989 Air gaps between copper lines
Methods are described for forming "air gaps" between adjacent copper lines on patterned substrates. The common name "air gap" will be used interchangeably the...
US-9,396,988 Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns
A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening...
US-9,396,987 Method for fabricating a substrate and semiconductor structure
The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an...
US-9,396,986 Mechanism of forming a trench structure
Forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer involves performing an implant to generate passages in the upper...
US-9,396,985 Element isolation structure of semiconductor and method for forming the same
Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor...
US-9,396,984 Method of producing a microelectronic device in a monocrystalline semiconductor substrate with isolation...
A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline...
US-9,396,983 Susceptor
A susceptor, comprises: a base part; multiple holders distributed on the base part for accommodating wafers; an inner ring connected to the base part; and an...
US-9,396,982 Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof
A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed...
US-9,396,981 Vacuum treatment apparatus
To reduce pumping time of a vacuum treatment chamber served by a transport arrangement in a transport chamber the vacuum treatment chamber is split into a...
US-9,396,980 Anti-electrostatic substrate cassette
The present invention provides an anti-electrostatic cassette, which mainly comprises at least an electrostatic discharge (ESD) device connected electrically to...
US-9,396,979 Wafer carrier including air filters
A wafer carrier comprises a body part constructed and arranged to accommodate a wafer and including first and second layers which are stacked in sequence. A...
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