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Patent # Description
US-9,396,169 Combination book with e-book using color space encoded image with color correction using a pseudo-euclidean...
Embodiments of the present disclosure can include systems, methods, and non-transitory computer program products for using color space encoded images to publish...
US-9,396,168 System and method for using data and angles to automatically generate a narrative story
A system and method for automatically generating a narrative story receives data and information pertaining to a domain event. The received data and information...
US-9,396,167 Template-based page layout for hosted social magazines
Page layout of content items from a variety of sources is performed. A content processing system queues content items, such as user-generated blogs, tweets,...
US-9,396,166 System and method for structuring speech recognized text into a pre-selected document format
A system for creating a structured report using a template having at least one predetermined heading and formatting data associated with each heading. The steps...
US-9,396,165 Information display system, information display apparatus, information display method, information display...
The present invention includes: receiving, from a terminal, display position information for specifying a display area 31 of content information displayed on a...
US-9,396,164 Sparsity-driven matrix representation to optimize operational and storage efficiency
Embodiments of the invention relate to sparsity-driven matrix representation. In one embodiment, a sparsity of a matrix is determined and the sparsity is...
US-9,396,163 Mixing optimal solutions
This invention relates to a method, system and computer program product for selecting an optimized solution in a computerised multiple-constraint problem space,...
US-9,396,162 Method and apparatus for estimating the state of a system
Disclosed herein are methods, apparatuses, and techniques for estimating the state of a system. According to one implementation, a Massively Parallel Nested...
US-9,396,161 Method and system for managing hardware resources to implement system functions using an adaptive computing...
An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The...
US-9,396,160 Automated test generation service
Systems and methods are described for testing computing resources. In one embodiment, a request for verification of a computing setting related to a computing...
US-9,396,159 Simple, reliable, connectionless communication mechanism
A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages....
US-9,396,158 Stream application performance monitoring metrics
Techniques are disclosed for calculating performance metrics associated with a data stream. A processing element configured to process data tuples flowing...
US-9,396,157 Stream application performance monitoring metrics
Techniques are disclosed for calculating performance metrics associated with a data stream. A processing element configured to process data tuples flowing...
US-9,396,156 System and method for socially organized storage and shared access to storage appliances
In various embodiments, the present invention relates to systems and methods for managing user data in a plurality of storage appliances coupled to a wide area...
US-9,396,155 Envelope detection device and related communication device
An envelope detection device for detecting a transmission signal of a high speed serial communication includes: an operation circuit, for receiving the...
US-9,396,154 Multi-core processor for managing data packets in communication network
A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a...
US-9,396,153 Data communication interface for an agricultural utility vehicle
A data communication interface for an agricultural utility vehicle, particularly an agricultural tractor, having an interface connector that can be connected...
US-9,396,152 Device, system and method for communication with heterogenous physical layers
A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device...
US-9,396,151 PCI express tunneling over a multi-protocol I/O interconnect
Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for...
US-9,396,150 Computer system and method utilizing a PCIe switch to control transfer of packets
A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O...
US-9,396,149 PCIE switch apparatus and method of controlling connection thereof
The present invention relates to a PCIe switch apparatus and a method of controlling the connection thereof. The PCIe switch apparatus includes a PCIe...
US-9,396,148 System method for connecting USB Type-C devices by measuring predetermined test patterns between a plurality of...
In some example embodiments, there may be provided a method, which may include sending, by a user equipment, a first predetermined test pattern to a first...
US-9,396,147 Interconnection of peripheral devices on different electronic devices
A method and apparatus of performing a data transmission from an electronic device or a peripheral device of an electronic device to a peripheral device of a...
US-9,396,146 Timing-budget-based quality-of-service control for a system-on-chip
A system-on-chip including an ingress arbiter module to receive a plurality of service requests from a plurality of devices located upstream to access a...
US-9,396,145 In-chip bus tracer
A single integrated circuit comprises one or more functional modules; a bus port; a bus in communication with the one or more functional modules and the bus...
US-9,396,144 High speed data transmission
A data reception circuit removes reliance on stacked transistors providing analog logic processing. A first trigger element outputs an up signal in response to...
US-9,396,143 Hierarchical in-memory sort engine
A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure...
US-9,396,142 Virtualizing input/output interrupts
An input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrupts or...
US-9,396,141 Memory system and information processing device by which data is written and read in response to commands from...
According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second...
US-9,396,140 Method and apparatus for transferring frames with different world wide name addresses and connection rates...
A system including a memory with arrays, a register, and a port. The memory stores an interrupt service routine (ISR). The arrays store respective fields. The...
US-9,396,139 System and method of connecting a computer to a peripheral of another computer
A system and method of connecting a computer to a peripheral of another computer. An example system includes a processor connected to a network and to the one...
US-9,396,138 Parallel block allocation for declustered logical disks
In a method for allocating space on a logical disk, a computer receives an allocation request to allocate a number of requested logical disk extents. The...
US-9,396,137 Storage device, protection method, and electronic apparatus
According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input...
US-9,396,136 Cascaded data encryption dependent on attributes of physical memory
Apparatus and method for providing data security through cascaded encryption. In accordance with various embodiments, input data are encrypted in relation to a...
US-9,396,135 Method and apparatus for improving computer cache performance and for protecting memory systems against some...
A physical cache memory that is divided into one or more virtual segments using multiple circuits to decode addresses is provided. An address mapping and an...
US-9,396,134 Authorization logic in memory constrained security device
Architecture that utilizes logical combinations (e.g., of Boolean logic) of authorizations as a logical authorization expression that is computed through a...
US-9,396,133 Caching scheme synergy for extent migration between tiers of a storage system
A method according to one embodiment includes determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system,...
US-9,396,132 Storage control device and system to improve data retention in variable resistance memory cells
Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value...
US-9,396,131 Dynamic three-tier data storage utilization
A system for dynamically utilizing data storage comprises a processor and a memory. The processor is configured to determine whether a data storage criterion is...
US-9,396,130 System translation look-aside buffer integrated in an interconnect
System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB...
US-9,396,129 Synchronous and asynchronous discard scans based on the type of cache memory
A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space....
US-9,396,128 System and method for dynamic allocation of unified cache to one or more logical units
A system and method provide a unified cache in a Small Computer System Interface (SCSI) device which can be dynamically allocated to one or more Logical Units...
US-9,396,127 Synchronizing access to data in shared memory
In some embodiments, in response to execution of a load-reserve instruction that binds to a load target address held in a store-through upper level cache, a...
US-9,396,126 Clearing an application cache
A system and machine-implemented method for clearing an application cache. A request for a manifest file is received from an electronic device, the manifest...
US-9,396,125 Dynamic management of memory ranges exempted from cache memory access
A computer-implemented method for defining transient-access memory ranges of a block of memory includes retrieving, via a processor, a plurality of memory...
US-9,396,124 Apparatus and method for configurable redundant fuse banks
An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of...
US-9,396,123 Core-specific fuse mechanism for a multi-core die
An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled...
US-9,396,122 Cache allocation scheme optimized for browsing applications
Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of...
US-9,396,121 Managing sequentiality of tracks for asynchronous PPRC tracks on secondary
For performing efficient management of tracks in an asynchronous Peer-to-Peer Redundant Copy (PPRC) operation in a computing storage environment, a correct...
US-9,396,120 Adjustable over-restrictive cache locking limit for improved overall performance
Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache....
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