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Patent # Description
US-9,401,381 Solid-state image pickup device
A portion on the light exit end surface side of a fiber optic plate includes a first portion and a second portion. The first portion corresponds to a peripheral...
US-9,401,380 Backside structure and methods for BSI image sensors
A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal...
US-9,401,379 Image sensor module and method for producing such a module
An image sensor module includes an image sensor bearer and an image sensor, the image sensor bearer being fashioned as an injection-molded circuit bearer, and...
US-9,401,378 Solid-state imaging device and method for manufacturing solid-state imaging device
According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes a photoelectric conversion element, a floating...
US-9,401,377 Infrared detector made up of suspended bolometric micro-plates
An array bolometric detector for detecting an electromagnetic radiation in a predetermined infrared or terahertz wavelength range, including a substrate, and an...
US-9,401,376 Thin film transistor and active matrix organic light emitting diode assembly and method for manufacturing the same
The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The...
US-9,401,375 Display panel and display device
A display panel and a display are disclosed. A display panel has an active area and a peripheral area disposed adjacent to the active area and comprises a first...
US-9,401,374 Pixel structure, dual gate pixel structure and display device
According to the present disclosure, there are disclosed a pixel structure, a dual-gate pixel structure and a display device. The pixel structure comprises: a...
US-9,401,373 Multi-fin finFETs with merged-fin source/drains and replacement gates
A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the...
US-9,401,372 Dual isolation on SSOI wafer
A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET)...
US-9,401,371 Sacrificial spin-on glass for air gap formation after bl isolation process in single gate vertical channel 3D...
A method for manufacturing a memory device, which can be configured as a 3D NAND flash memory, and includes a plurality of stacks of conductive strips,...
US-9,401,370 Non-volatile memory device and method for fabricating the same
A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL)...
US-9,401,369 Memory device and method for fabricating the same
A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of...
US-9,401,368 Memory device and method for forming the same
Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells...
US-9,401,367 Nonvolatile memory cell with improved isolation structures
An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration...
US-9,401,366 Layout pattern for 8T-SRAM and the manufacturing method thereof
The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second...
US-9,401,365 Epitaxial source/drain differential spacers
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over...
US-9,401,364 Semiconductor device, electronic component, and electronic device
A semiconductor device has a function of storing data and includes an output terminal, a first terminal, a second terminal, a first circuit, and second...
US-9,401,363 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
US-9,401,362 Multiple threshold voltage semiconductor device
In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, a second field effect...
US-9,401,361 Semiconductor arrangement having first semiconductor device over first shallow well having first conductivity...
A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second...
US-9,401,360 Semiconductor devices including etching stop films
A semiconductor device may include a substrate including an NMOS region and a PMOS region. A gate structure can include a gate pattern and a spacer pattern,...
US-9,401,359 Semiconductor device
A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate...
US-9,401,358 Semiconductor device structure
A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different...
US-9,401,357 Directional FinFET capacitor structures
A method for fabricating a capacitor within a FinFET device includes patterning a first gate interconnect material having a first recess. The method also...
US-9,401,356 Power circuit, control method, power system, and package structure of power circuit
A power circuit, control method, power system, and package structure of power circuit are disclosed. The power circuit includes a quasi-cascade power unit. The...
US-9,401,355 Semiconductor device including a diode arranged in a trench
One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from...
US-9,401,354 Display panel having a reduced dead space
A display panel includes a substrate including a display area displaying an image and a peripheral area. A plurality of shorting bar connection parts are formed...
US-9,401,353 Interposer integrated with 3D passive devices
An integrated interposer includes an interposer substrate including at least a first portion of a 3D passive device within an active region of the interposer...
US-9,401,352 Field-effect device and manufacturing method thereof
Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region,...
US-9,401,351 Electronic device for ESD protection
An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is...
US-9,401,350 Package-on-package (POP) structure including multiple dies
A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID...
US-9,401,349 Stack of integrated-circuit chips and electronic device
A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each...
US-9,401,348 Method of making a substrate structure having a flexible layer
There is provided a semiconductor light emitting device including: a heat dissipation structure including one or more of materials among a metal, a ceramic, a...
US-9,401,347 Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of...
A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in...
US-9,401,346 Optical bus in 3D integrated circuit stack
An optical bus of an integrated circuit comprises: a polymer waveguide, a micromirror, and an optical coupler. The polymer waveguide is disposed in a via formed...
US-9,401,345 Semiconductor device package with organic interposer
A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on...
US-9,401,344 Substrates with transferable chiplets
A method for fabricating a substrate having transferable chiplets includes forming a photo-sensitive adhesive layer on a process side of a source substrate...
US-9,401,343 Method of processing a semiconductor wafer
A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices...
US-9,401,342 Semiconductor package having wire bond wall to reduce coupling
A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the...
US-9,401,341 Electronic devices and components for high efficiency power circuits
An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is...
US-9,401,340 Semiconductor device and ceramic circuit substrate, and producing method of semiconductor device
A semiconductor device comprises a circuit layer composed of a conductive material, and a semiconductor element mounted on the circuit layer, wherein an...
US-9,401,339 Wafer level packages having non-wettable solder collars and methods for the fabrication thereof
Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes...
US-9,401,338 Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is...
US-9,401,337 Molding structure for wafer level package
Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound...
US-9,401,336 Dual layer stack for contact formation
A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact...
US-9,401,335 Semiconductor device and electronic apparatus
A semiconductor device that is connected to a wiring substrate includes a semiconductor substrate, a circuit provided on the semiconductor substrate, a...
US-9,401,334 Preventing unauthorized use of integrated circuits for radiation-hard applications
An integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard...
US-9,401,333 Semiconductor device
According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding...
US-9,401,332 Method for manufacturing semiconductor device and alignment mark of semiconductor device
According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell...
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