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Patent # Description
US-9,401,331 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a...
US-9,401,330 IC package with non-uniform dielectric layer thickness
An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that...
US-9,401,329 Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an...
US-9,401,328 Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the...
An electric contact structure includes a first structural layer; a second structural layer made of dielectric material extending over the first structural...
US-9,401,326 Split contact structure and fabrication method thereof
A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a...
US-9,401,325 Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The...
US-9,401,324 Semiconductor device having an on die termination circuit
According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of...
US-9,401,323 Protected through semiconductor via (TSV)
A semiconductor structure having a through semiconductor via (TSV) which includes a semiconductor wafer of a semiconductor material and having a front side and...
US-9,401,322 Semiconductor devices and structures thereof
A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material...
US-9,401,321 Display device
A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a...
US-9,401,320 Combined substrate
A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second...
US-9,401,319 Semiconductor device
A semiconductor device is provided, in which a first lead (11) is joined with the bottom electrode (23) of a MOS-FET (21) with first solder (51), the top...
US-9,401,318 Quad flat no-lead package and manufacturing method thereof
A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip...
US-9,401,317 Heat sink mount and assembly
An assembly for a heat sink having a contact plate with opposing first and second faces, a plurality of fins extending from the first face of the contact plate,...
US-9,401,316 Electronic devices with improved thermal performance
Electronic devices with improved thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed....
US-9,401,315 Thermal hot spot cooling for semiconductor devices
A semiconductor device package which includes a semiconductor package, a semiconductor device joined to the semiconductor package; and a lid to be placed over...
US-9,401,314 Method of testing semiconductor device
A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having...
US-9,401,313 Automated optical inspection of unit specific patterning
A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed...
US-9,401,312 TSV redundancy scheme and architecture using decoder/encoder
A method of redirecting signal bits associated with or corresponding to defective TSVs of a TSV array to a row or a column of redundant TSVs in the TSV array...
US-9,401,311 Self aligned structure and method for high-K metal gate work function tuning
A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a...
US-9,401,310 Method to form trench structure for replacement channel growth
Embodiments may include a method of semiconductor patterning including forming a first trench bordered by a first spacer material. The method may involve...
US-9,401,309 Multiheight contact via structures for a multilevel interconnect structure
Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer...
US-9,401,308 Packaging devices, methods of manufacture thereof, and packaging methods
Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate...
US-9,401,307 Method forming through-via using electroless plating solution
The present invention provides a method for forming a through-via, including the steps of (1) forming an alloy film as a diffusion-preventive layer that...
US-9,401,306 Self-aligned capillarity-assisted microfabrication
A manufacturing process, which we term Self-Aligned Capillarity-Assisted Lithography for manufacturing devices having nano-scale or micro-scale features, such...
US-9,401,305 Air gaps structures for damascene metal patterning
A pattern of parallel lines defines first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being...
US-9,401,304 Patterning method for low-k inter-metal dielectrics and associated semiconductor device
Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant...
US-9,401,303 Handler wafer removal by use of sacrificial inert layer
The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a...
US-9,401,302 FinFET fin bending reduction
An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a...
US-9,401,301 Semiconductor device having a gate that is buried in an active region and a device isolation film
A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining...
US-9,401,300 Media substrate gripper including a plurality of snap-fit fingers
One aspect of an assembly configured to grip a substrate includes a gripper including a first finger and a second finger, a first chuck body snap-fit to the...
US-9,401,299 Support for semiconductor substrate
A moveable semiconductor substrate support includes a control device receiving data from one or more sensors and providing control signals to one or more...
US-9,401,298 Method and device for transferring a chip to a contact substrate
A method and device for transferring a chip (18) situated on a transfer substrate (26) to a contact substrate (50), and for contacting the chip with the contact...
US-9,401,297 Electrostatic chuck mechanism and charged particle beam apparatus
Proposed are an electrostatic chuck mechanism and a charged particle beam apparatus including a first plane that is a plane of a side in which a sample is...
US-9,401,296 Vacuum robot adapted to grip and transport a substrate and method thereof with passive bias
A vacuum robot adapted to grip and transport a substrate. The robot includes a robot drive coupled to an arm and having an end-effector adapted to support the...
US-9,401,295 Load port apparatus and clamping device to be used for the same
To suppress deformation of a portion to be clamped even when a load applied to the portion to be clamped is increased at the time of fixing a front opening...
US-9,401,294 Compact substrate transport system
A substrate processing system including a load port module configured to hold at least one substrate container for storing and transporting substrates, a...
US-9,401,293 Polishing apparatus and polishing method
A polishing apparatus for polishing a substrate includes a polishing table holding a polishing pad, a top ring configured to press the substrate against the...
US-9,401,292 Transporting device for substrate of liquid crystal display and using method thereof
A transporting device for transporting substrate of liquid crystal display and using method thereof are provided. The transporting device comprises a fixing...
US-9,401,291 Coating apparatus
A coating apparatus includes: a slit nozzle including a retention chamber that retains the coating material; a moving mechanism that moves the slit nozzle; a...
US-9,401,290 Semiconductor apparatus and method for producing the same
A method for producing a semiconductor apparatus with a mold including an upper mold half and a lower mold half, includes: an arranging step of arranging on one...
US-9,401,289 Semiconductor device and method of backgrinding and singulation of semiconductor wafer while reducing kerf...
A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active...
US-9,401,288 Low CTE interposer
An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to...
US-9,401,287 Methods for packaging integrated circuits
Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the...
US-9,401,286 Plasma processing apparatus
Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on...
US-9,401,285 Chemical mechanical planarization topography control via implant
Systems and methods for chemical mechanical planarization topography control via implants are disclosed. In one embodiment, a method of manufacturing a...
US-9,401,284 Semiconductor device
A semiconductor device includes: a substrate comprised by gallium arsenide; an active layer provided on the substrate; a first nickel-plated layer provided on a...
US-9,401,283 Substrate treatment method
A substrate treatment method includes the steps of: supporting a substrate with a support member; arranging an extension surface such that the extension surface...
US-9,401,282 Method of manufacturing semiconductor device, cleaning method, substrate processing apparatus and...
Provided is a method of manufacturing a semiconductor device, which efficiently removes a high permittivity film (high-k film). The method of manufacturing a...
US-9,401,281 Mask set for fabricating integrated circuits and method of fabricating integrated circuits
A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality...
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