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Patent # Description
US-9,401,230 Cu-Ni-Si-Co copper alloy for electronic materials and manufacturing method thereof
Cu--Ni--Si--Co copper alloy strip having excellent balance between strength and electrical conductivity which can prevent the drooping curl is provided. The...
US-9,401,229 Inspection apparatus for penetration pipe of nuclear reactor head
An inspection apparatus for a penetration pipe of a nuclear reactor head comprising: a body; a probe module installed at the body and having a probe which is...
US-9,401,228 Standing wave nuclear fission reactor and methods
Disclosed embodiments include nuclear fission reactor cores, nuclear fission reactors, methods of operating a nuclear fission reactor, and methods of managing...
US-9,401,227 Post package repair device
A post package repair device may include a plurality of bank groups, each of the plurality of bank groups including fuses indicating repair information,...
US-9,401,226 MRAM initialization devices and methods
A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region...
US-9,401,225 Timing-drift calibration
The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a...
US-9,401,224 Monitoring device of integrated circuit
A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad...
US-9,401,223 At-speed test of memory arrays using scan
A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory...
US-9,401,222 Determining categories for memory fail conditions
Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention...
US-9,401,221 Sampling circuit
Sampling is continuously performed at high speed with a simple sampling circuit including a polarity switcher to invert or non-invert the polarity of an input...
US-9,401,220 Multi-phase gate driver and display panel using the same
A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to...
US-9,401,219 Electronic fuse semiconductor device for selecting failed redundancy word lines
A semiconductor device with a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to a level...
US-9,401,218 Fuse circuit and semiconductor apparatus including the same
A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch...
US-9,401,217 Flash memory with improved read performance
A non-volatile memory device includes an array of memory cells and a plurality of word lines and voltage supply lines. Each memory cell of the array is coupled...
US-9,401,216 Adaptive operation of 3D NAND memory
In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current...
US-9,401,215 Nonvolatile memory device and method for driving the same
A method for driving a nonvolatile memory device includes performing an erase operation with respect to a plurality of memory cells, stopping the erase...
US-9,401,214 Three-dimensional memory device and operating method of a storage device including the same
A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a...
US-9,401,213 Non-volatile memory apparatus and operation method thereof
A NVM apparatus and an operation method thereof are provided. The NVM apparatus includes a NVM cell, a programming voltage generator, a WL-voltage generator and...
US-9,401,212 Mitigation of data retention drift by programming neighboring memory cells
A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge...
US-9,401,211 Method of manufacturing semiconductor device
Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first...
US-9,401,210 Nonvolatile memory device and programming method thereof including common source line feedback during program...
A nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a CSL driver, and control logic. The memory cell array...
US-9,401,209 Three-dimensional semiconductor memory device
A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to...
US-9,401,208 Magnetic random access memory cell with a dual junction for ternary content addressable memory applications
An MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a...
US-9,401,207 Pseudo SRAM using resistive elements for non-volatile storage
A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current...
US-9,401,206 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material...
A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the...
US-9,401,205 Electronic device
An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a...
US-9,401,204 Electronic device and method for operating electronic device
An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response...
US-9,401,203 Memory driving circuit
A memory driving circuit includes a current source configured to output a second current, a first switching unit configured to undergo switching to connect to...
US-9,401,202 Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to...
US-9,401,201 Write driver for memory
A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline,...
US-9,401,200 Memory cells with p-type diffusion read-only port
A memory cell includes a bistable element and two p-channel transistors (i.e., first and second p-channel transistors). The bistable element includes a...
US-9,401,199 Eight transistor soft error robust storage cell
A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage...
US-9,401,198 Non-volatile dynamic random access memory (NVDRAM)
A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to...
US-9,401,197 Memory devices, systems and methods employing command/address calibration
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test...
US-9,401,196 Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data
Read-only ("RO") data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as...
US-9,401,195 Self-referenced sense amplifier for spin-torque MRAM
Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random...
US-9,401,194 Fast programming of magnetic random access memory (MRAM)
A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access...
US-9,401,193 Memory device refreshing word line accessed in previous write operation
A memory device includes a memory bank including a plurality of word lines, and a word line controller capable of activating a first word line, which is...
US-9,401,192 Ferroelectric memory device and timing circuit to control the boost level of a word line
A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The...
US-9,401,191 Semiconductor memory apparatus
A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a...
US-9,401,190 High speed FPGA boot-up through concurrent multi-frame configuration scheme
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant...
US-9,401,189 Methods and apparatus for performing runtime data eye monitoring and continuous data strobe calibration
Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and...
US-9,401,188 Devices and systems including enabling circuits
Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices,...
US-9,401,187 Integrated circuit and precharge/active flag generation circuit
An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to...
US-9,401,186 Semiconductor memory apparatus and data transmission
A semiconductor memory apparatus may include a data pad and a shared transmission line. The shared transmission line may be configured to transmit data received...
US-9,401,185 Sense amplifier and semiconductor device including the same
A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified...
US-9,401,184 Memory system and method for power management
A memory system and method for power management are disclosed. In one embodiment, a variable credit value that indicates an amount of power currently available...
US-9,401,183 Stacked integrated memory device
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that...
US-9,401,182 Rack mount device
A rack mount device comprising: a housing; first and second drawer sections to be withdrawable from the housing; storage sections provided in the first and...
US-9,401,181 Electronic device with locking structure for storage device
A locking structure for detachably mounting a storage device to a casing of an electronic device includes a carrier fixed in the casing which defines a...
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