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Patent # Description
US-9,406,823 Methods for fabricating self-aligning semiconductor hetereostructures using nanowires
Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.
US-9,406,822 Polishing coated substrates
A process for the production of an optoelectronic device, such as a photovoltaic cell or a light emitting diode is disclosed. The process comprises providing a...
US-9,406,821 Method of fabricating a back-contact solar cell and device thereof
Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type...
US-9,406,820 Method for fabricating photovoltaic cells with plated contacts
The disclosed technology relates generally to photovoltaic cells, and more particularly to photovoltaic cells with plated metal contacts. In one aspect, a...
US-9,406,819 Photovoltaic component with a high conversion efficiency
A photovoltaic component that includes at least one first array of photovoltaic nano-cells is disclosed. Each photovoltaic component includes an optical...
US-9,406,818 Chip package and method of manufacturing the same
A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of...
US-9,406,817 Lead frame package for solar concentrators
Techniques for providing high-capacity, re-workable connections in concentrated photovoltaic devices are provided. In one aspect, a lead frame package for a...
US-9,406,816 Solid-state imaging apparatus, method of manufacturing solid-state imaging apparatus and electronic device
Provided is a solid-state imaging apparatus including: a plurality of photoelectric conversion units; an element isolation unit that performs element isolation...
US-9,406,815 Adding decoupling function for TAP cells
A circuit includes a tap cell. The tap cell includes a well region, a first well pickup region in the well region, a VDD power rail and a VSS power rail spaced...
US-9,406,814 Non-volatile memory device
According to one embodiment, a non-volatile memory device includes a first stacked electrode provided above a underlying layer, a second stacked electrode...
US-9,406,813 Semiconductor device and method of manufacturing same
To provide a semiconductor device with nonvolatile memory, having improved performance. A memory cell has control and memory gate electrodes on a semiconductor...
US-9,406,812 Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
A nonvolatile memory ("NVM") bitcell includes a source and a drain formed in an active region of a substrate and separated by a channel region in the active...
US-9,406,811 Nonvolatile semiconductor memory device including a charge storage layer formed on first and second insulating...
According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on...
US-9,406,810 Semiconductor device and manufacturing method thereof
In a semiconductor device, a region where a channel is formed is protected. In a semiconductor device, a region protecting a region where a channel is formed is...
US-9,406,809 Field-effect transistor
There is provided a field effect transistor having, on a substrate, at least a gate electrode, a gate insulating film, an active layer mainly containing an...
US-9,406,808 Semiconductor device, display device, and electronic appliance
In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is...
US-9,406,807 Crystallization method of thin film transistor, thin film transistor array panel and manufacturing method for...
Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and...
US-9,406,806 Semiconductor element and display device using the same
A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate...
US-9,406,805 Fin-FET
A Fin-FET and a method of forming the Fin-FET are provided. A substrate is provided, and then a mask layer is formed thereabove. A first trench is formed in the...
US-9,406,804 FinFETs with contact-all-around
An integrated circuit structure includes a semiconductor substrate, a semiconductor fin over the semiconductor substrate, a gate stack on a top surface and a...
US-9,406,803 FinFET device including a uniform silicon alloy fin
A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the...
US-9,406,801 FinFET
A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric...
US-9,406,800 Body-tied, strained-channel multi-gate device and methods of manufacturing same
A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor...
US-9,406,799 High mobility PMOS and NMOS devices having Si--Ge quantum wells
At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device....
US-9,406,798 Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by...
US-9,406,797 Semiconductor integrated circuit with dislocations
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over...
US-9,406,796 Semiconductor device
A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and...
US-9,406,795 Trench gate MOSFET
A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a...
US-9,406,794 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of...
US-9,406,793 Semiconductor device with a vertical channel formed through a plurality of semiconductor layers
Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and...
US-9,406,792 Semiconductor device having GaN-based layer
A semiconductor device according to an embodiment includes a first semiconductor layer of a first GaN based semiconductor, a second semiconductor layer of a...
US-9,406,791 Transistors, semiconductor devices, and methods of manufacture thereof
Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device...
US-9,406,790 Suspended ring-shaped nanowire structure
A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single...
US-9,406,789 Nanoscale variable resistor/electromechanical transistor
A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic...
US-9,406,788 Structure of a trench MOS rectifier and method of forming the same
A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n- drift epitaxial layer, a...
US-9,406,787 Semiconductor device including an IGBT as a power transistor
An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an...
US-9,406,786 Method for manufacturing semiconductor device
In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film...
US-9,406,785 Thin film transistor and method of forming the same
A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide...
US-9,406,784 Method of manufacturing isolation structure and non-volatile memory with the isolation structure
A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive...
US-9,406,783 Method to induce strain in finFET channels from an adjacent region
Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different...
US-9,406,782 Structure and method for FinFET device
A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer...
US-9,406,781 Thin film transistor
Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented...
US-9,406,780 Semiconductor device and method
Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer...
US-9,406,779 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,406,778 Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The...
US-9,406,777 Method for manufacturing a transistor device
A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially...
US-9,406,776 High temperature gate replacement process
A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate...
US-9,406,775 Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints
Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a...
US-9,406,774 Field effect transistor and method of making
A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the...
US-9,406,773 Semiconductor device and method of manufacturing the same
A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode...
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