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Patent # Description
US-9,406,772 Semiconductor structure with a multilayer gate oxide and method of fabricating the same
A semiconductor structure with a multilayer gate oxide is provided. The structure includes a substrate. A multilayer gate oxide is disposed on the substrate,...
US-9,406,771 Semiconductor structure and manufacturing method thereof
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion...
US-9,406,770 Method of fabricating semiconductor device having a resistor structure
Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming...
US-9,406,769 Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
US-9,406,768 Semiconductor device
A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of...
US-9,406,767 POC process flow for conformal recess fill
A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a...
US-9,406,766 Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell...
US-9,406,765 Hybrid dielectric non-volatile memory with nano particles (Si/SiO.sub.2 core/shell) as charge trapping layer
Si/SiO.sub.2 core/shell nanostructures with sizes below 30 nm as trapping points in UV curable hybrid organic-inorganic gate dielectrics are presented in order...
US-9,406,764 Simple and cost-free MTP structure
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate...
US-9,406,763 Stress-reduced field-effect semiconductor device and method for forming therefor
A field-effect semiconductor device is provided. The field-effect semiconductor device includes a semiconductor body with a first surface defining a vertical...
US-9,406,762 Semiconductor device with junction termination extension
A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first...
US-9,406,761 Semiconductor device and manufacturing method thereof
A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state...
US-9,406,760 Semiconductor film, transistor, semiconductor device, display device, and electronic appliance
Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One...
US-9,406,759 Methods for forming nanocrystals with position-controlled dopants
A doping method using a three-step synthesis to make high-quality doped nanocrystals is provided. The first step includes synthesizing starting host particles....
US-9,406,758 Semiconductor devices with sharp gate edges and methods to fabricate same
This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate...
US-9,406,757 Semiconductor device and method of manufacturing semiconductor device
The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a...
US-9,406,756 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor-device manufacturing method of the present invention includes a step of selectively implanting impurity ions into a surface of an SiC...
US-9,406,755 Smart semiconductor switch
A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has...
US-9,406,754 Smart semiconductor switch
A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor...
US-9,406,753 Semiconductor devices including superlattice depletion layer stack and related methods
A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a...
US-9,406,752 FinFET conformal junction and high EPI surface dopant concentration method and device
A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a...
US-9,406,751 Method for making strained semiconductor device and related methods
A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal...
US-9,406,750 Output capacitance reduction in power transistors
Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased...
US-9,406,749 Method of manufacturing a horizontal gate-all-around transistor having a fin
A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a...
US-9,406,748 Perfectly shaped controlled nanowires
A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric...
US-9,406,747 Component in the form of a wafer level package and method for manufacturing same
A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the...
US-9,406,746 Work function metal fill for replacement gate fin field effect transistor process
A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the...
US-9,406,745 Method of manufacturing super junction for semiconductor device
A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a...
US-9,406,744 Semiconductor device having a breakdown voltage holding region
A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the...
US-9,406,743 Semiconductor device with counter doped layer
A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n.sup.+-type source layer on a surface of an n.sup.--type...
US-9,406,742 Semiconductor device having super-junction structures
A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second...
US-9,406,741 Thin film resistor having improved power handling capability
Designs and methodologies related to attenuators having a thin-film resistor assembly are disclosed. In some embodiments, the thin-film assembly can include a...
US-9,406,740 Silicon process compatible trench magnetic device
A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls...
US-9,406,739 Inductor system and method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors....
US-9,406,738 Inductive structure formed using through silicon vias
An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a...
US-9,406,737 Display device having particular insulating layer
A display device is disclosed, which comprises: a first substrate; a first insulating layer disposed on the first substrate; a second insulating layer disposed...
US-9,406,736 Organic light-emitting display apparatus
An organic light-emitting display apparatus includes a thin film transistor including an active layer, gate, source and drain electrodes, a first insulating...
US-9,406,735 Organic light-emitting display apparatus with enhanced light output efficiency and manufacturing method thereof
An organic light-emitting display apparatus includes: a first substrate; a display unit on the first substrate, the display unit being divided into a pixel unit...
US-9,406,734 Foldable display device
A foldable display device includes display panel and a driving circuit on a flexible substrate. The display panel includes at least one bendable area and a flat...
US-9,406,733 Pixel structure
A pixel structure, including a data line, a scan line, at least one active device, a first auxiliary electrode, and a light emitting device, is provided. The at...
US-9,406,732 Organic light emitting diode display device and fabricating method thereof
An OLED display device is discussed which can include: a first substrate defined into an emission region and a non-emission region; a first electrode formed on...
US-9,406,731 Display device
A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed...
US-9,406,730 Thin film transistor and organic light emitting device including polycrystalline silicon layer
A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the...
US-9,406,729 Organic light emitting diode display device and method for repairing organic light emitting diode display
An organic light emitting diode (OLED) display includes a light-emitting region including an organic emission layer and a non-light-emitting region neighboring...
US-9,406,727 Dual-mode pixels including emissive and reflective devices, and dual-mode display using the pixels
A dual-mode display including a substrate and a plurality of sub-pixels on the substrate, in which each sub-pixel includes, a reflective device having an...
US-9,406,726 Dual-mode pixels including emissive and reflective devices, and dual-mode display using the pixels
A dual-mode display including a substrate and a multiple sub-pixels on the substrate, in which each sub-pixel includes, a color selection reflector, and an...
US-9,406,725 Display device and method for manufacturing display device
The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced....
US-9,406,724 Organic light-emitting diode (OLED) display with microlens below color filters and method of manufacturing the same
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes an OLED comprising a plurality of pixels configured to...
US-9,406,723 Organic light emitting diode display and method for manufacturing the same
An organic light emitting diode display having a pixel array structure capable of maximizing space use, and a method for manufacturing the same. The organic...
US-9,406,722 Solid-state imaging device and method of manufacturing the same
A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on...
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