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Patent # Description
US-9,406,721 Memory device
A memory device includes a bit line extending in a first direction, a word line extending in a second direction crossing the first direction, an insulating...
US-9,406,720 Semiconductor storage device
A memory includes first to fifth WLs extending in a first-direction. First to fourth element-regions extend in a tilt-direction. The first to fourth...
US-9,406,719 Light-emitting structure
A light-emitting structure, comprising a substrate; a first unit and a second unit, separately formed on the substrate; a trench between the first unit and the...
US-9,406,718 Image sensor pixel cell with non-destructive readout
A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate...
US-9,406,717 Passivation of back-illuminated image sensor
A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped...
US-9,406,716 Infrared reflection/absorption layer for reducing ghost image of infrared reflection noise and image sensor...
An image sensor includes a photosensing element for receiving infrared (IR) radiation and detecting the IR radiation and generating an electrical signal...
US-9,406,715 Image sensor device
An image sensor device comprises an isolation well region within a substrate. A gate stack is over the isolation well region on the first surface of the...
US-9,406,714 Unit pixel with photodiode under gate of sensing transistor and image pixel array including the same
A unit pixel includes a sensing transistor, a photo diode, and a reset drain region. The sensing transistor includes a reference active region, an output active...
US-9,406,713 Vertically stacked image sensor
A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate...
US-9,406,712 Interconnect structure for connecting dies and methods of forming the same
A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first...
US-9,406,711 Apparatus and method for backside illuminated image sensors
A backside illuminated image sensor comprises a photodiode and a first transistor located in a first substrate, wherein the first transistor is electrically...
US-9,406,710 Semiconductor device and manufacturing method of the same
A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a...
US-9,406,709 Methods for fabricating and using nanowires
Methods, apparatuses, systems, and devices relating to fabricating one or more nanowires are disclosed. One method for fabricating a nanowire includes:...
US-9,406,708 Image sensor devices and methods for fabricating the same
The present invention provides an image sensor device including a substrate, a channel formed in the substrate, a photoelectric transfer region formed in the...
US-9,406,707 Solid-state image pickup element and image pickup apparatus
Disclosed herein is a solid-state image pickup element, including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity...
US-9,406,706 Manufacturing method of semiconductor device
It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at...
US-9,406,705 Display backplane having multiple types of thin-film-transistors
There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the...
US-9,406,704 Thin film transistor array panel
A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the...
US-9,406,703 Flexible display device and curved display device
Provided is a configuration for a semiconductor layer and a line for reducing the segment length of the semiconductor layer with respect to the bending...
US-9,406,702 Array substrate, method for fabricating the same and display device
An array substrate, a method for fabricating the same and a display device as provided relate to the field of display technologies and can overcome the...
US-9,406,701 Array substrate and method for fabricating the same, and display device
The present invention provides an array substrate comprising a plurality of data lines, a plurality of gate lines and a plurality of oxide thin film...
US-9,406,700 Thin film transistors with oxide semiconductor having low resistance patterns with oxygen deficiencies
A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide...
US-9,406,699 Semiconductor device, and display device and electronic device having the same
An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a...
US-9,406,698 Display device and manufacturing method thereof
A display device in which reliability of a display element is improved is provided. Alternatively, a display device in which reliability of a transistor is...
US-9,406,697 Semiconductor devices and manufacturing methods thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first fin field effect transistor...
US-9,406,696 High-frequency device including high-frequency switching circuit
A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency...
US-9,406,695 Circuit and method for improving ESD tolerance and switching speed
Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor...
US-9,406,694 Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a metal layer containing boron, a semiconductor film extending in a direction intersecting with a...
US-9,406,693 Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory
Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory...
US-9,406,692 Vertical-type non-volatile memory devices having dummy channel holes
A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are...
US-9,406,691 Non-volatile memory device
According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and...
US-9,406,690 Contact for vertical memory with dopant diffusion stopper and associated fabrication method
A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of...
US-9,406,689 Logic finFET high-K/conductive gate embedded multiple time programmable flash memory
A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type....
US-9,406,688 Vertical structure non-volatile memory device having insulating regions that are formed as air gaps
A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that...
US-9,406,687 Integration of memory devices with different voltages
Device and method for forming a device are presented. The method includes providing a substrate prepared with at least a memory cell region having first and...
US-9,406,686 Memory cell comprising non-self-aligned horizontal and vertical control gates
The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above...
US-9,406,685 Flash memory unit and memory array, and programming, erasing and reading method thereof
A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second...
US-9,406,684 Semiconductor device including an electrode lower layer and an electrode upper layer and method of...
The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has...
US-9,406,683 Wet bottling process for small diameter deep trench capacitors
A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on...
US-9,406,682 Method and structure for preventing epi merging in embedded dynamic random access memory
After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a...
US-9,406,681 Memory cell
Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell...
US-9,406,680 Semiconductor device including fin structures and manufacturing method thereof
A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a...
US-9,406,679 Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited...
US-9,406,678 Method and gate structure for threshold voltage modulation in transistors
A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold...
US-9,406,677 Semiconductor devices and fabrication method thereof
A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one...
US-9,406,676 Method for forming single diffusion breaks between finFET devices and the resulting devices
A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the...
US-9,406,675 FinFET structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the...
US-9,406,674 Integrated III-nitride D-mode HFET with cascoded pair half bridge
There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a...
US-9,406,673 Semiconductor component with transistor
One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor...
US-9,406,672 Capacitor arrays for minimizing gradient effects and methods of forming the same
Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of...
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