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Patent # Description
US-9,406,620 Semiconductor package
A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted...
US-9,406,619 Semiconductor device including pre-fabricated shielding frame disposed over semiconductor die
A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through...
US-9,406,618 Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and...
An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a...
US-9,406,617 Structure and process for W contacts
Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes...
US-9,406,616 Merged source/drain and gate contacts in SRAM bitcell
A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first...
US-9,406,615 Techniques for forming interconnects in porous dielectric materials
Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer...
US-9,406,614 Material and process for copper barrier layer
A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material...
US-9,406,613 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,406,612 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,406,611 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,406,610 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,406,609 Opening structure and manufacturing method thereof and interconnection structure
In a manufacturing method of an opening structure, a multi-layer structure including alternately stacked conductive layers and first dielectric layers is formed...
US-9,406,608 Dummy metal structure and method of forming dummy metal structure
Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal...
US-9,406,607 Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode,...
US-9,406,606 Semiconductor device having a reduced area and enhanced yield
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power...
US-9,406,605 Integrated circuit with guard ring
An integrated circuit includes a circuit and a guard ring. The circuit is over a substrate. The guard ring surrounds the circuit and includes a staggered line....
US-9,406,604 Vertically oriented semiconductor device and shielding structure thereof
The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor...
US-9,406,603 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically...
US-9,406,602 Electronic device
In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an...
US-9,406,601 Body-bias voltage routing structures
Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an...
US-9,406,600 Printed circuit board and stacked semiconductor device
A semiconductor package includes an interposer and a semiconductor element mounted on one surface of the interposer. A plurality of lands are formed on another...
US-9,406,599 Wiring substrate and method for manufacturing wiring substrate
A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes...
US-9,406,598 Package with a fan-out structure and method of forming the same
An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the...
US-9,406,597 Integrated circuit system with distributed power supply comprising interposer and voltage regulator
An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit...
US-9,406,596 Molding compound structure
A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first...
US-9,406,595 Semiconductor package
A semiconductor package includes a die pad, wherein a semiconductor die is mounted on the die pad; a plurality of leads comprising a power lead disposed along a...
US-9,406,594 Leadframe based light emitter components and related methods
Leadframe based light emitter components and methods are provided. In some aspects, a leadframe based light emitter component includes a leadframe element, an...
US-9,406,593 Lead frame, electric power converting device, semiconductor apparatus and method of manufacturing semiconductor...
According to the disclosure, a lead frame is provided, which includes: a first island and a second island that are arranged side by side; an outer peripheral...
US-9,406,592 Conductor strip with contact areas having cutouts
A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one...
US-9,406,591 Semiconductor device and method for manufacturing the same
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating...
US-9,406,590 Chip package and manufacturing method thereof
A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The...
US-9,406,589 Via corner engineering in trench-first dual damascene process
An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the...
US-9,406,588 Semiconductor package and manufacturing method thereof
The present disclosure provides a semiconductor structure. The semiconductor structure includes a carrier, a first redistribution layer (RDL) over the carrier,...
US-9,406,587 Substrate conductor structure and method
Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods...
US-9,406,586 Cooling jacket and electronic device having the same
A cooling jacket includes: first and second pipe portions through which a coolant flows; and a main portion connected with side surfaces of the first and second...
US-9,406,585 Liquid-cooled-type cooling device
A liquid-cooled-type cooling device includes a casing which has a cooling-liquid inlet formed at a rear end portion of the casing and a cooling-liquid outlet...
US-9,406,584 Semiconductor package and method for manufacturing the same
A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second...
US-9,406,583 COF type semiconductor package and method of manufacturing the same
Provided is a chip on film (COF) type semiconductor package. The COF type semiconductor device includes a flexible film, an electrode pattern formed on the...
US-9,406,582 Apparatus to minimize thermal impedance using copper on die backside
A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen...
US-9,406,581 Methods of packaging semiconductor devices and structures thereof
Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes...
US-9,406,580 Packaging for fingerprint sensors and methods of manufacture
A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the...
US-9,406,579 Semiconductor device and method of controlling warpage in semiconductor package
A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the...
US-9,406,578 Chip package having extended depression for electrical connection and method of manufacturing the same
A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The...
US-9,406,577 Wafer stack protection seal
A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and...
US-9,406,576 Semiconductor device
A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the...
US-9,406,575 Pixel array substrate and display panel
A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source,...
US-9,406,574 Oxide formation in a plasma process
A method of making a semiconductor structure is provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in...
US-9,406,573 Exposure mask fabrication method, exposure mask fabrication system, and semiconductor device fabrication method
An exposure mask fabrication method includes measuring and storing defect position data, for each EUV exposure mask blank, that indicates the position of at...
US-9,406,572 Method for processing a substrate and a method of process screening for integrated circuits
According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may...
US-9,406,571 Method for manufacturing semiconductor device including inline inspection
A method for manufacturing a semiconductor device includes: forming a semiconductor wafer including a plurality of semiconductor devices sandwiching a dicing...
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