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Patent # Description
US-9,405,715 Host computer and method for managing SAS expanders of SAS expander storage system
In a method for managing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to an SAS expander...
US-9,405,714 Method and apparatus for managing sensor data and method and apparatus for analyzing sensor data
Provided are an apparatus and method for transmitting only sensor data actually used to process a user request among sensor data received from a sensor when...
US-9,405,713 Commonality of memory island interface and structure
The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh...
US-9,405,712 On-chip traffic prioritization in memory
According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing...
US-9,405,711 On-chip traffic prioritization in memory
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a...
US-9,405,710 Systems and methods for providing interactive media guidance on a wireless communications device
A wireless communications device provides users with opportunities to access interactive media guidance or other applications and to control interactive media...
US-9,405,709 Systems and methods for performing copy-on-write operations
A computer-implemented method for performing copy-on-write operations may include (1) identifying a write operation addressed to at least a part of a storage...
US-9,405,708 Preventing attacks that rely on same-page merging by virtualization environment guests
In a virtualization environment, a guest process may protect itself from potential timing side-channel attacks by other guest processes on the same host machine...
US-9,405,707 Secure replay protected storage
Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such...
US-9,405,706 Instruction and logic for adaptive dataset priorities in processor caches
A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The...
US-9,405,705 Hierarchical data storage system
A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main...
US-9,405,704 Establishing a point-in-time copy relationship between source logical addresses and target logical addresses
Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target...
US-9,405,703 Translation lookaside buffer
The described embodiments include a translation lookaside buffer ("TLB") that is used for performing virtual address to physical address translations when...
US-9,405,702 Caching TLB translations using a unified page table walker cache
A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a...
US-9,405,701 Apparatus and method for accelerating operations in a processor which uses shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
US-9,405,700 Methods and apparatus for virtualization in an integrated circuit
Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an...
US-9,405,699 Systems and methods for optimizing computer performance
In one embodiment, a method includes initiating execution of an application, the application utilizing a hash table data structure to map a plurality of keys to...
US-9,405,698 System and methods for memory expansion
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from...
US-9,405,697 Memory management method and apparatus
A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in...
US-9,405,696 Cache and method for cache bypass functionality
A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with...
US-9,405,695 Cache modeling using random sampling and a timestamp histogram
A system and method for determining an optimal cache size of a computing system is provided. In some embodiments, the method comprises selecting a portion of an...
US-9,405,694 Caching data between a database server and a storage system
Techniques are provided for using an intermediate cache between the shared cache of an application and the non-volatile storage of a storage system. The...
US-9,405,693 Non-volatile memory cache performance improvement
In order to provide a more efficient persistent storage device, one or more long-term storage media are included along with a non-volatile memory. In one...
US-9,405,692 Data processing performance enhancement in a distributed file system
Systems and methods of data processing performance enhancement are disclosed. One embodiment includes, invoking operating system calls to optimize cache...
US-9,405,691 Locating cached data in a multi-core processor
Techniques described herein are generally related to managing cached memory addresses in a multi-core processor device that has a plurality of cores and a...
US-9,405,690 Method for storing modified instruction data in a shared cache
A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative...
US-9,405,689 Locally caching data from a shared storage
Systems, methods, and other embodiments associated with controlling when data blocks are cached at hosts from a shared storage are described. According to one...
US-9,405,688 Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and...
US-9,405,687 Method, apparatus and system for handling cache misses in a processor
In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion...
US-9,405,686 Cache allocation system and method using a sampled cache utility curve in constant space
Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache...
US-9,405,685 Method of providing content during hand-over and apparatus therefor
The present invention relates to a method and apparatus for providing mobile content to seamlessly transmit content to a mobile node even during a hand-over of...
US-9,405,684 System and method for cache management
A method, computer program product, and computing system for processing, on a host, a read request for a portion of a data file stored on a backend storage...
US-9,405,683 Processor and memory control method for allocating instructions to a cache and a scratch pad memory
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via...
US-9,405,682 Storage device access using unprivileged software code
A method and system for establishing more direct access to a storage device from unprivileged code are described. Using a storage infrastructure mechanism to...
US-9,405,681 Workload adaptive address mapping
Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request...
US-9,405,680 Communication-link-attached persistent memory system
A system and method is described that accesses a network persistent memory unit (nPMU). One embodiment comprises a primary region corresponding to a predefined...
US-9,405,679 Determining a location of a memory device in a solid state device
A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that...
US-9,405,678 Flash memory controller with calibrated data communication
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal...
US-9,405,677 Dynamic tuning of internal parameters for solid-state disk based on workload access patterns
A system and method for tuning a solid state disk memory includes computing a metric representing a usage trend of a solid state disk memory. Whether one or...
US-9,405,676 Devices and methods for operating a solid state drive
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired...
US-9,405,675 System and method for managing execution of internal commands and host commands in a solid-state memory
Embodiments of the invention are directed to enable simultaneous or nearly simultaneous execution of internal and host-issued commands in a non-volatile storage...
US-9,405,674 Address generating circuit and address generating method
An address generating circuit according to an embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines...
US-9,405,673 Memory controller, and electronic device having the same and method for operating the same
A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address...
US-9,405,672 Map recycling acceleration
An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source...
US-9,405,671 Process execution control based on the internal states of flash memories and power supply circuit information
Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the...
US-9,405,670 Wear leveling method and apparatus
The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical...
US-9,405,669 Recovery from cache and NVS out of sync
For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage...
US-9,405,668 Data storage device initialization information accessed by searching for pointer information
A data storage device including non-volatile storage is initialized from initialization information stored in an information initialization area. A pointer area...
US-9,405,667 Systems and methods for testing a software application
Systems, methods, and computer-readable media are disclosed for testing a software application. An exemplary method includes storing a control file identifying...
US-9,405,666 Health monitoring using snapshot backups through test vectors
Technologies are described for health monitoring using snapshot backups through test vectors. In some examples, health of an application deployed at a...
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