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Patent # Description
US-9,412,919 Light source circuit unit, illuminator, and display
Provided are a light source circuit unit that improves light extraction efficiency, as well as an illuminator and a display that include such a light source...
US-9,412,918 Light emitting device and method of manufacturing the same
A light emitting device includes a support member, a light emitting element, and an underfill material. The support member includes an insulating member and...
US-9,412,917 Light emitting device
This disclosure discloses a light-emitting device. The light-emitting device includes a transparent substrate with a recess and an upper surface; a wavelength...
US-9,412,916 Light source with quantum dots
The invention provides a luminescent nano particles based luminescent material comprising a matrix of interconnected coated luminescent nano particles, wherein...
US-9,412,915 Lighting apparatus
A lighting apparatus includes a substrate, a plurality of light-emitting dies disposed on the substrate and spaced apart from one another, a continuous...
US-9,412,914 Light emitting device
Provided is a light emitting device having a high light emitting efficiency and a good brightness distribution, further having a good color mixing and a good...
US-9,412,913 Slim LED package
Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on...
US-9,412,912 Method for transferring light-emitting elements onto a package substrate
A method for transferring light-emitting elements onto a package substrate includes: providing a light-emitting unit including a temporary substrate and...
US-9,412,911 Optical tuning of light emitting semiconductor junctions
Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the...
US-9,412,910 Semiconductor light emitting device and method for manufacturing same
According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor...
US-9,412,909 Light emitting apparatus, manufacturing method of light emitting apparatus, light receiving and emitting...
A manufacturing method is a method for manufacturing a light emitting apparatus including a translucent substrate, and a light emitting section and an optical...
US-9,412,908 Semiconductor light emitting device
Disclosed are a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a...
US-9,412,907 Graded vias for LED chip P- and N- contacts
The present disclosure provides various embodiments of light emitting chips and packages with improved current spreading structures, such as non-uniform via...
US-9,412,906 Light-emitting device
A light-emitting device comprises: a light-emitting stack comprising a first side, a second side opposite to the first side, and an upper surface between the...
US-9,412,905 White light emitting device
The present invention relates to a light-emitting device including a light source, a first light-emitting material spaced apart from the light source, and at...
US-9,412,904 Structured substrate for LEDs with high light extraction
A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host...
US-9,412,903 Semiconductor light emitting device
A semiconductor light emitting device includes a stacked semiconductor structure including a first conductivity-type semiconductor layer having a top surface...
US-9,412,902 Semiconductor structure with stress-reducing buffer structure
A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided....
US-9,412,901 Superlattice structure
A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different...
US-9,412,900 Green-light emitting device including quaternary quantum well on vicinal c-plane
Example embodiments relate to a green-light emitting device including a quaternary quantum well on a vicinal c-plane. The light-emitting device includes a...
US-9,412,899 Method of stress induced cleaving of semiconductor devices
A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress...
US-9,412,898 Apparatus and method of testing a substrate using a supporting nest and testing probes
Embodiments of the invention may provide a testing apparatus that is used to test solar cells or other electronic devices. The testing apparatus may comprise a...
US-9,412,897 Advanced hydrogenation of silicon solar cells
A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon...
US-9,412,896 Method for manufacturing solar cells, attenuating lid phenomena
To reduce degradation, by the LID effect, of the conversion efficiency of photovoltaic cells made of crystalline silicon, one or more steps of controlled...
US-9,412,895 Method of manufacturing photoelectric device
A method of manufacturing a photoelectric device, the method including: forming a first semiconductor layer on a semiconductor substrate through a first ion...
US-9,412,894 Photovoltaic device including gap passivation layer and method of manufacturing the same
A photovoltaic device includes a semiconductor substrate; an amorphous first conductive semiconductor layer on a first region of a first surface of the...
US-9,412,893 Solar module and process for production thereof
The present invention relates to a solar module comprising a first layer, a solar cell arranged above the first layer and a second layer arranged above the...
US-9,412,892 Vapor deposition apparatus and process for continuous indirect deposition of a thin film layer on a substrate
An apparatus and related process are provided for vapor deposition of a sublimated source material as a thin film on a photovoltaic (PV) module substrate. A...
US-9,412,891 Thermal receiver for high power solar concentrators and method of assembly
A device for dissipating heat from a photovoltaic cell is disclosed. A first thermally conductive layer receives heat from the photovoltaic cell and reduces a...
US-9,412,890 Photovoltaic module pin electrical connectors
Provided are novel structures for electrically interconnecting two or more building integrable photovoltaic (BIP) modules with a pin connector. Each module has...
US-9,412,889 Aligned networks on substrates
Among other things, two networks, one on top of the other, are formed on a substrate based on coating materials containing emulsions or foams. The two networks...
US-9,412,888 Solar cell and method for manufacturing the same
A solar cell includes a semiconductor substrate having a first conductivity type, an emitter layer on a surface of the semiconductor substrate, the emitter...
US-9,412,886 Electrical contact
A photovoltaic device with a low-resistance stable electrical back contact is disclosed. The photovoltaic device can have a CuTe.sub.x or CuTe.sub.xN.sub.y layer.
US-9,412,885 Solar cell
A solar cell can include a substrate of a first conductive type; an emitter region of a second conductive type opposite the first conductive type and which...
US-9,412,884 Module fabrication of solar cells with low resistivity electrodes
One embodiment of the present invention provides a solar module. The solar module includes a front-side cover, a back-side cover, and a plurality of solar cells...
US-9,412,883 Methods and apparatus for MOS capacitors in replacement gate process
Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor...
US-9,412,882 Schottky barrier diode
A Schottky barrier diode includes an n-type semiconductor layer including a Ga.sub.2O.sub.3-based compound semiconductor with n-type conductivity, and an...
US-9,412,881 Power device integration on a common substrate
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and...
US-9,412,880 Schottky diode with improved surge capability
An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package....
US-9,412,879 Integration of the silicon IMPATT diode in an analog technology
A method to integrate a vertical IMPATT diode in a planar process.
US-9,412,878 Semiconductor device and manufacturing method thereof
A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in...
US-9,412,877 Semiconductor device
A transistor or the like having excellent electrical characteristics is provided. A semiconductor device includes a gate electrode; a gate insulating film in...
US-9,412,876 Semiconductor device
The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first...
US-9,412,874 Semiconductor device
A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor...
US-9,412,873 Alignment features for improved alignment of layered components of a device display
Device display assemblies that include layered components provided with alignment features are disclosed. Protective sheets that are adhered to other layered...
US-9,412,872 N-type and P-type tunneling field effect transistors (TFETs)
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling...
US-9,412,871 FinFET with channel backside passivation layer device and method
A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside...
US-9,412,870 Device with engineered epitaxial region and methods of making same
A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the...
US-9,412,869 MOSFET with source side only stress
An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement...
US-9,412,868 Semiconductor device and fabrication method thereof
A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a...
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