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Patent # Description
US-9,412,867 Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of...
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate...
US-9,412,866 BEOL selectivity stress film
The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves...
US-9,412,865 Reduced resistance short-channel InGaAs planar MOSFET
A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a...
US-9,412,864 Junction-less transistors
A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming...
US-9,412,863 Enhanced breakdown voltages for high voltage MOSFETS
An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a...
US-9,412,862 Electronic device including a conductive electrode and a process of forming the same
An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a...
US-9,412,861 Semiconductor device having structure capable of suppressing oxygen diffusion and method of manufacturing the same
A semiconductor device is provided. The device includes a substrate; a gate dielectric film formed on the substrate; a gate electrode formed on the gate...
US-9,412,860 Multi-layer gate dielectric
A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second...
US-9,412,859 Contact geometry having a gate silicon length decoupled from a transistor length
Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure...
US-9,412,858 Group III nitride semiconductor device which can be used as a power transistor
A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the...
US-9,412,857 Nitride semiconductor device and method for manufacturing same
According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second...
US-9,412,856 Semiconductor device
A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride...
US-9,412,854 IGBT module and a circuit
An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a...
US-9,412,853 Protective device for a voltage-controlled semiconductor switch
A protective device for a voltage-controlled semiconductor switch has a gate connection, a power emitter connection, an auxiliary emitter connection and a...
US-9,412,852 Low-temperature fabrication of nanomaterial-derived metal composite thin films
Disclosed are new methods of fabricating nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400.degree. C.). The...
US-9,412,851 Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed...
A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the...
US-9,412,850 Method of trimming fin structure
A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy...
US-9,412,849 Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes forming first and second fin-type structures on first and second regions of a substrate, respectively,...
US-9,412,848 Methods of forming a complex GAA FET device at advanced technology nodes
The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a...
US-9,412,847 Self-aligned passivation of active regions
A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species,...
US-9,412,846 Thin-film transistor, method of manufacturing the same, and organic light-emitting diode (OLED) display...
A thin-film transistor, method of manufacturing the same, and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the...
US-9,412,845 Dual gate structure
Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that...
US-9,412,844 Trench power MOSFET
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the...
US-9,412,843 Method for embedded diamond-shaped stress element
A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A...
US-9,412,842 Method for fabricating semiconductor device
A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second...
US-9,412,841 Method of fabricating a transistor using contact etch stop layers
A method for fabricating a field-effect transistor includes forming a spacer adjacent to sidewalls of a gate structure. The method further includes forming...
US-9,412,840 Sacrificial layer for replacement metal semiconductor alloy contact formation
A sacrificial layer is formed on exposed surfaces of source/drain structures that are located at the footprint of a gate stack. A stack of, from bottom to top,...
US-9,412,839 Methods of forming replacement gate structures on FinFET devices and the resulting devices
One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper...
US-9,412,838 Ion implantation methods and structures thereof
A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins....
US-9,412,837 Methods of manufacturing semiconductor devices
In a method of manufacturing a semiconductor device, the method comprises: forming a dummy gate pattern on a substrate; and forming first spacers at side...
US-9,412,836 Contacts for transistors
The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact...
US-9,412,835 Rectifier structures with low leakage
An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over...
US-9,412,834 Method of manufacturing HEMTs with an integrated Schottky diode
A method of manufacturing a transistor device includes forming a compound semiconductor material on a semiconductor carrier, forming a source region and a drain...
US-9,412,833 Narrow semiconductor trench structure
Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first...
US-9,412,832 Semiconductor device and semiconductor device manufacturing method
In aspects of the invention, an n-type epitaxial layer that forms an n.sup.- type drift layer is formed on the upper surface of an n-type semiconductor...
US-9,412,831 Manufacturing method for silicon carbide semiconductor device
In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a...
US-9,412,830 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a...
US-9,412,829 Method for fabricating semiconductor device and semiconductor device
A method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and...
US-9,412,828 Aligned gate-all-around structure
A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode...
US-9,412,827 Vertical semiconductor device having semiconductor mesas with side walls and a PN-junction extending between...
A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially...
US-9,412,826 Method for manufacturing semiconductor device using a semiconductor substrate including silicon and a first...
A method for manufacturing a semiconductor device includes processes of: (a) implant first conductivity type first impurities in a first region of a first...
US-9,412,825 Semiconductor device
A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based...
US-9,412,824 Semiconductor component having a dopant region formed by a dopant composed of an oxygen/vacancy complex
A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant...
US-9,412,823 Semiconductor device and method of manufacturing the same
A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type...
US-9,412,822 Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material,...
US-9,412,821 Stacked thin channels for boost and leakage improvement
A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar...
US-9,412,820 Semiconductor device with thinned channel region and related methods
A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above...
US-9,412,819 Semiconductor device and manufacturing method thereof
In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating...
US-9,412,818 System and method of manufacturing a fin field-effect transistor having multiple fin heights
An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a...
US-9,412,817 Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel...
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