Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,412,766 Semiconductor device and manufacturing method of the same
An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source...
US-9,412,765 Thin film transistor, manufacturing method of same, and display device
According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain...
US-9,412,764 Semiconductor device, display device, and electronic device
To prevent an influence of normally-on characteristics of the transistor which a clock signal is input to a terminal of, a wiring to which a first low power...
US-9,412,763 Display device and electronic unit
A display device includes a substrate, a display element, a transistor as a drive element of the display element, and a holding capacitance element holding...
US-9,412,762 DC-DC converter and semiconductor device
A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control...
US-9,412,761 Array substrate, method for manufacturing the same and display apparatus
An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode...
US-9,412,760 Array substrate and manufacturing method thereof, and display device
An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region...
US-9,412,759 CMOS gate contact resistance reduction
A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate...
US-9,412,758 Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication
A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over...
US-9,412,757 Semiconductor device
A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact...
US-9,412,756 Nonvolatile semiconductor memory device including pillars buried inside through holes same
In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and...
US-9,412,755 Manufacturing method for semiconductor device
In a manufacturing method for a semiconductor device provided with a MONOS-type FET for a non-volatile memory and high-voltage and low-voltage MOSFETs, a groove...
US-9,412,754 Semiconductor memory device and production method thereof
A semiconductor memory device includes a silicon substrate having an impurity diffusion region, and a memory cell array. The memory cell array includes...
US-9,412,753 Multiheight electrically conductive via contacts for a multilevel interconnect structure
A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a...
US-9,412,752 Reference line and bit line structure for 3D memory
A 3D NAND flash memory includes even and odd stacks of conductive strips. Some of the conductive strips in the stacks are configured as word lines. Data storage...
US-9,412,751 Electronic device
An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively...
US-9,412,750 Fabrication method and structure of semiconductor non-volatile memory device
A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor...
US-9,412,749 Three dimensional memory device having well contact pillar and method of making thereof
A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type...
US-9,412,748 Method of manufacturing semiconductor device having an implanting from a second direction inclined relative to...
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode...
US-9,412,747 Semiconductor device and a method of manufacturing the same
A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged...
US-9,412,746 Anti-fuses on semiconductor fins
A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A...
US-9,412,745 Semiconductor structure having a center dummy region
A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a...
US-9,412,744 III-V CMOS integration on silicon substrate via embedded germanium-containing layer
After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a...
US-9,412,743 Complementary metal oxide semiconductor device
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which...
US-9,412,742 Layout design for manufacturing a memory cell
A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active...
US-9,412,741 Integration of analog transistor
An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of...
US-9,412,740 Integrated circuit product with a gate height registration structure
One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second...
US-9,412,739 Semiconductor device
A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor...
US-9,412,738 Semiconductor device
A semiconductor device includes a semiconductor substrate of a first conductivity type, an impurity layer of a second conductivity type provided within the...
US-9,412,737 IGBT with a built-in-diode
When an IGBT has a barrier layer 10 that separates an upper body region 8a from a lower body region 8b, conductivity modulation is enhanced and on-resistance...
US-9,412,736 Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations...
US-9,412,734 Structure with inductor and MIM capacitor
A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the...
US-9,412,733 MOSFET with integrated schottky diode
Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each...
US-9,412,732 Semiconductor device
In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a...
US-9,412,731 Semiconductor device
Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active...
US-9,412,730 Integrated circuits, standard cells, and methods for generating a layout of an integrated circuit
An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells...
US-9,412,729 Semiconductor package and fabricating method thereof
A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package...
US-9,412,728 Post-CMOS processing and 3D integration based on dry-film lithography
A method for performing a post processing pattern on a diced chip having a footprint, comprises the steps of providing a support wafer; applying a first dry...
US-9,412,727 Printing transferable components using microstructured elastomeric surfaces with pressure modulated reversible...
In a method of printing a transferable component, a stamp including an elastomeric post having three-dimensional relief features protruding from a surface...
US-9,412,726 Display device
A display device includes a substrate on which a plurality of pixels are arranged and a circuit for displaying images with respect to each pixel is formed, a...
US-9,412,725 Method and apparatus for image sensor packaging
Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are...
US-9,412,724 Chip-scale packaged LED device
An LED device includes a substrate, a number (N) of flip-chip LED die(s), an electrical conductive structure and a lens structure. The substrate has upper and...
US-9,412,723 Package on-package structures and methods for forming the same
A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further...
US-9,412,722 Multichip stacking package structure and method for manufacturing the same
The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package...
US-9,412,721 Contactless communications using ferromagnetic material
A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the...
US-9,412,720 Semiconductor package having supporting plate and method of forming the same
A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging...
US-9,412,719 3DIC interconnect apparatus and method
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed...
US-9,412,718 3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of...
Methods are provided to operate a processor device in one of multiple power operating modes. The processor device comprises first and second processor chips...
US-9,412,717 Apparatus and methods for molded underfills in flip chip packaging
Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase...
US-9,412,716 Semiconductor package and method for manufacturing the same
A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.