Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,412,715 Semiconductor device, electronic device, and semiconductor device manufacturing method
A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a...
US-9,412,714 Wire bond support structure and microelectronic package including wire bonds therefrom
A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least...
US-9,412,713 Treatment method of electrodeposited copper for wafer-level-packaging process flow
A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a...
US-9,412,712 Semiconductor package and method of manufacturing the same
A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads...
US-9,412,711 Electronic device
The present invention provides an electronic device that is able to achieve an improvement in yield or an electronic device that is able to prevent a sealing...
US-9,412,710 Semiconductor device
In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that...
US-9,412,709 Semiconductor structure with sacrificial anode and passivation layer and method for forming
A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the...
US-9,412,708 Enhanced ESD protection of integrated circuit in 3DIC package
Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of...
US-9,412,707 Method of manufacturing semiconductor package
Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which...
US-9,412,706 Engineered carrier wafers
Apparatuses and methods for reducing the warp of semiconductor wafer stacks during manufacturing are disclosed. An engineered carrier wafer is disclosed. The...
US-9,412,705 Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible...
A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers...
US-9,412,703 Chip package structure having a shielded molding compound
A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection...
US-9,412,702 Laser die backside film removal for integrated circuit (IC) packaging
Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die...
US-9,412,701 Semiconductor device including a DC-DC converter
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS.cndot.FET for a high side switch and a power...
US-9,412,700 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over...
US-9,412,699 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,412,698 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,412,697 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,412,696 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,412,695 Interconnect structures and methods of fabrication
Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a...
US-9,412,694 Polysilicon fuse, manufacturing method thereof, and semiconductor device including polysilicon fuse
A polysilicon fuse is disclosed that is capable of securing good insulation after being cut into small areas. A manufacturing method for the fuse and a...
US-9,412,693 Semiconductor device having jumper pattern and blocking pattern
A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer...
US-9,412,692 Flexible microsystem structure
A flexible microsystem structure is provided. The flexible microsystem structure includes a flexible substrate; and a chip disposed over the flexible substrate,...
US-9,412,691 Chip carrier with dual-sided chip access and a method for testing a chip using the chip carrier
Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface,...
US-9,412,690 Package substrates, packages including the same, methods of fabricating the packages with the package...
A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip...
US-9,412,689 Semiconductor packaging structure and method
A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A...
US-9,412,688 Wiring board
The wiring board of the present invention includes at least one insulating layer and at least one conductor layer being alternately laminated, a semiconductor...
US-9,412,687 Wiring substrate and method of manufacturing the same
A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring...
US-9,412,686 Interposer structure and manufacturing method thereof
The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a...
US-9,412,685 Semiconductor device and method of manufacturing the same
A semiconductor device having a substrate including a plurality of external terminals on a rear surface and a plurality of bonding terminals electrically...
US-9,412,684 Top exposed semiconductor chip package
A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top...
US-9,412,683 Semiconductor device having barrier metal layer
According to one embodiment, a semiconductor device having an interlayer insulating film, a molybdenum containing layer, a barrier metal layer and a plug...
US-9,412,682 Through-silicon via access device for integrated circuits
A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor...
US-9,412,681 Interposer device
The invention relates to an interposer device comprising a doped silicon substrate (1) having an epitaxial layer (24) on a first side and two through vias (11,...
US-9,412,680 Semiconductor module and electrically-driven vehicle
A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the...
US-9,412,679 Power semiconductor device
An insulating substrate includes a base portion that is made of metal and serves as a radiating surface, an insulating layer, and a circuit pattern. The...
US-9,412,678 Structure and method for 3D IC package
A chip package may include: a first die; a second die; an underfill disposed between and in physical contact with the first die and the second die; and one or...
US-9,412,677 Computer systems having an interposer including a flexible material
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-9,412,676 Ceramic package
A ceramic package includes a package main body which is formed of a ceramic material, which has a front surface and a back surface having a rectangular shape in...
US-9,412,675 Interconnect structure with improved conductive properties and associated systems and methods
Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive...
US-9,412,674 Shielded wire arrangement for die testing
An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage...
US-9,412,673 Multi-model metrology
Disclosed are apparatus and methods for characterizing a plurality of structures of interest on a semiconductor wafer. A plurality of models having varying...
US-9,412,672 In situ etch compensate process
A method includes performing an etching on a mask layer to form an opening in the mask layer. The mask layer is a part of a wafer. The method further includes...
US-9,412,671 Method for controlling processing temperature in semiconductor fabrication
A method for controlling processing temperature in semiconductor fabrication is provided. The method includes detecting temperature in a first chamber...
US-9,412,670 System, method and apparatus for RF power compensation in plasma etch chamber
A system and method of applying power to a target plasma chamber include, characterizing a no plasma performance slope of the target plasma chamber, applying a...
US-9,412,669 Semiconductor device and a method of manufacturing the same
A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a...
US-9,412,668 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,412,667 Asymmetric high-k dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,412,666 Equal gate height control method for semiconductor device with different pattern densites
A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having...
US-9,412,665 Semiconductor device and method of fabricating the same
A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.