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Dual material finFET on single substrate
A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second...
Dies for RFID devices and sensor applications
Deep reactive ion silicon etching of a device wafer, laser-induced release of individual dies, and individual placement of the dies on flexible substrates...
Structure and approach to prevent thin wafer crack
A semiconductor structure and a method of manufacture are provided. Devices, such as integrated circuit dies, are mounted on a substrate, such as another die,...
Method for forming package-on-package structure
A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second...
Methods of forming V0 structures for semiconductor devices that includes
recessing a contact structure
One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate...
Semiconductor structure having source/drain gouging immunity
There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region....
Constrained nanosecond laser anneal of metal interconnect structures
In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the...
Method for manufacturing semiconductor device
In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV...
Reverse tone self-aligned contact
Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The...
Forming merged lines in a metallization layer by replacing sacrificial
lines with conductive lines
A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a...
Graphene sacrificial deposition layer on beol copper liner-seed for
mitigating queue-time issues between liner...
After forming a copper seed layer on a diffusion barrier layer present on sidewalls and a bottom surface of at least one opening, a graphene sacrificial layer...
Through silicon via (TSV) process
A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a...
Air gap forming techniques based on anodic alumina for interconnect
An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to...
Air-gap formation in interconnect structures
A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall...
Interconnect structure and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a...
Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which...
Via patterning using multiple photo multiple etch
A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a...
Via definition scheme
A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop...
Via in substrate with deposited layer
An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which...
Semiconductor devices and structures
A method for fabricating semiconductor devices, including: providing a CMOS fabric and metal layers, the metal layers including a first metal layer, a second...
Integrated circuit assembly and method of making
A first wafer is provided that includes an insulating layer, a first active layer, and a handle layer. The insulating layer has a first surface and a second...
Shallow trench isolation for end fin variation control
A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a...
Semiconductor device, module and system each including the same, and
method for manufacturing the semiconductor...
A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact...
FinFET having controlled dielectric region height
Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one...
Semiconductor device including substrate contact and related method
A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at...
Method of using separate wafer contacts during wafer processing
Embodiments of the invention are directed towards improving on-wafer process performance and processing at increased processing fluid/wafer temperature while...
End effector pads
An end effector pad including a fence member, a first recessed support member extending from a first side of the fence member, a second recessed support member...
Device wafer processing method
A device wafer includes a device area where a plurality of devices are formed on the front side of the device wafer and a peripheral marginal area surrounding...
Methods for processing substrates
A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the...
Electrostatic chuck device
An electrostatic chuck device includes an electrostatic chuck part that has an upper surface as a placement surface for placing a plate-shaped sample and has an...
Atmosphere replacement apparatus, substrate transport apparatus, substrate
transport system, and EFEM
The present invention provides an atmosphere replacement apparatus capable of replacing the atmosphere on the surface of a wafer with a small amount of gas. The...
Workpiece transfer system
The present application provides a workpiece transfer system in which a production efficiency of a production line to be used can be improved. For example, a...
A reticle pod includes an outer pod shell and an outer pod door disposed under the outer pod shell. The outer pod door has at least one gas control hole. A seal...
Ceiling storage device capable of wafer purging
The invention provides an apparatus for stocking and purging a wafer at a ceiling. The apparatus includes: a rail that is formed so as to be installed on a...
Securing mechanism and method for wafer bonder
Disclosed are various features associated with a securing mechanism for a wafer bonder. In certain situations, operation of securing mechanisms can generate...
Wafer bonding for 3D device packaging fabrication
An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a...
Acid treatment strategies useful to fabricate microelectronic devices and
A method of treating one or more wafers is provided. The method comprises the steps of: a) providing at least one wafer, that has first and second opposed...
Liquid processing method and liquid processing apparatus
A surface of a substrate can be dried cleanly after liquid-processed by a liquid processing method and a liquid processing apparatus. The liquid processing...
Method for manufacturing a chip arrangement
A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the...
Molded insulator in package assembly
Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material....
Integrated circuit packaging system with substrate and method of
An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the...
Metal oxide TFT with improved source/drain contacts and reliability
A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material...
Epitaxial silicon wafer and method for manufacturing same
An epitaxial silicon wafer cut from a silicon single crystal grown by the Czochralski method, and having a diameter of 300 mm or more. In this epitaxial silicon...
Semiconductor device and method for forming the same
A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in...
Three-dimensional integrated circuit device fabrication including wafer
Method and Apparatus so configured for the fabrication of three-dimensional integrated devices. A crystalline substrate within an area of a donor semiconductor...
Method of outgassing a mask material deposited over a workpiece in a
Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention...
Pattern forming method
A pattern forming method of forming a pattern on an underlying layer of a target object includes forming a block copolymer layer, which includes a first polymer...
Plasma processing method and plasma processing apparatus
Plasma etching is performed while suppressing bowing during etching of a multi-layer film. The plasma etching is performed multiple times using a processing gas...
Methods of forming single and double diffusion breaks on integrated
circuit products comprised of FinFET...
One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of...
Patterning method and semiconductor structure including forming a
plurality of holes using line pattern masks
A patterning method is provided. A substrate including a material layer thereon is provided. A patterned hard mask layer, having a plurality of first holes, is...