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Patent # | Description |
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US-9,412,614 |
Nano wire structure and method for fabricating the same A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a... |
US-9,412,613 |
Development of high etch selective hardmask material by ion implantation
into amorphous carbon films Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to... |
US-9,412,612 |
Method of forming semiconductor device A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are... |
US-9,412,611 |
Use of grapho-epitaxial directed self-assembly to precisely cut lines A method for forming a patterned topography on a substrate is provided. The substrate is initially provided with an exposed plurality of lines formed atop. An... |
US-9,412,610 |
Semiconductor devices and methods of manufacturing the same A method of manufacturing a semiconductor device is disclosed. In the method, a substrate having a first surface and a second surface is provided. The second... |
US-9,412,609 |
Highly selective oxygen free silicon nitride etch A method for selectively etching silicon nitride with respect to silicon oxide is provided. An oxygen free silicon nitride etch gas comprising H.sub.2 and... |
US-9,412,608 |
Dry-etch for selective tungsten removal Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten... |
US-9,412,607 |
Plasma etching method An isotropic etching process can be performed with high uniformity. A plasma etching method of etching an etching target layer containing silicon includes... |
US-9,412,606 |
Target dimension uniformity for semiconductor wafers One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to... |
US-9,412,605 |
Method of removing oxide on semiconductor surface by layer of sulfur Embodiments of the present disclosure relate generally to a method of passivating and/or removing oxides on a semiconductor surface by using ammonium sulfide,... |
US-9,412,604 |
Methods of manufacturing semiconductor device The present inventive concept provides methods of manufacturing a semiconductor device including forming an inner mask layer on an etching target film, the... |
US-9,412,603 |
Trimming silicon fin width through oxidation and etch Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a... |
US-9,412,602 |
Deposition of smooth metal nitride films In one aspect, methods of forming smooth ternary metal nitride films, such as Ti.sub.xW.sub.yN.sub.z films, are provided. In some embodiments, the films are... |
US-9,412,601 |
Method for processing a carrier A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent... |
US-9,412,600 |
Method of forming a semiconductor structure including a ferroelectric
material and semiconductor structure... An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a... |
US-9,412,599 |
Manufacturing method for semiconductor device A gate oxide film is formed in a region having a MOSFET on a semiconductor substrate formed therein, and a first polysilicon film serving as a gate electrode of... |
US-9,412,598 |
Edge rounded field effect transistors and methods of manufacturing Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking... |
US-9,412,597 |
Flash memory semiconductor device and method thereof The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array... |
US-9,412,596 |
Nitridation on HDP oxide before high-k deposition to prevent oxygen
ingress A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device... |
US-9,412,595 |
Systems and methods for intelligent dispatching for wafer processing Systems and methods are provided for ion implantation. For example, ion implantation is performed using a first ion implant tool. At least one condition... |
US-9,412,594 |
Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a... |
US-9,412,593 |
Composition for film formation, resist underlayer film, and forming method
of resist underlayer film, and... A composition for film formation includes a compound represented by formula (1), and a solvent. R.sup.1 represents a monovalent group including an aromatic... |
US-9,412,592 |
Imprint mask, method for manufacturing the same, and method for
manufacturing semiconductor device According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on... |
US-9,412,591 |
Process of semiconductor fabrication with mask overlay on pitch multiplied
features and associated structures Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The... |
US-9,412,590 |
Manufacturing method of oxide semiconductor device A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is... |
US-9,412,589 |
Method for fabricating NMOS and PMOS transistors on a substrate of the
SOI, in particular FDSOI, type and... An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region,... |
US-9,412,588 |
Method of growing nitride semiconductor layer and nitride semiconductor
formed by the same A method of growing a nitride semiconductor layer includes forming a plurality of nano-structures on a substrate, forming a first buffer layer on the substrate... |
US-9,412,587 |
Method of manufacturing semiconductor device, substrate processing
apparatus, gas supply system, and recording... A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a... |
US-9,412,586 |
Method for producing a template for epitaxial growth having a sapphire
(0001) substrate, an initial-stage A1N... A surface of a sapphire (0001) substrate is processed to form recesses and protrusions so that protrusion tops are flat and a given plane-view pattern is... |
US-9,412,585 |
Method of manufacturing a SiOCN film, substrate processing apparatus, and
recording medium A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by... |
US-9,412,584 |
Method of manufacturing a thin film having a high tolerance to etching and
non-transitory computer-readable... A thin film containing boron and a borazine ring structure is formed on a substrate by performing a cycle a predetermined number of times under a condition... |
US-9,412,583 |
Methods of forming dielectric layers and methods of manufacturing
semiconductor devices using the same To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a... |
US-9,412,582 |
Reaction tube, substrate processing apparatus, and method of manufacturing
semiconductor device A structure for constituting a process chamber in which a plurality of substrates is processed by reacting a predetermined precursor gas therein includes an... |
US-9,412,581 |
Low-K dielectric gapfill by flowable deposition Methods are described for forming a flowable low-k dielectric layer on a patterned substrate. The film may be a silicon-carbon-oxygen (Si--C--O) layer in which... |
US-9,412,580 |
Methods for forming group III-nitride materials and structures formed by
such methods Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The... |
US-9,412,579 |
Methods and apparatus for controlling substrate uniformity A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically... |
US-9,412,578 |
Charged particle analysers and methods of separating charged particles A method of separating charged particles using an analyzer is provided, the method comprising: causing a beam of charged particles to fly through the analyzer... |
US-9,412,577 |
Vacuum ultraviolet photoionization and chemical ionization combined ion
source for mass spectrometry This invention relates to the field of mass spectrometry, and more specifically to a vacuum ultraviolet photoionization and chemical ionization combined ion... |
US-9,412,576 |
Ion trap mass spectrometer using cold electron source The present invention relates to an ion trap mass spectrometer using a cold electron source, in a production of a portable mass spectrometer, in which a... |
US-9,412,575 |
Ion guide with orthogonal sampling A mass spectrometer is disclosed comprising a RF ion guide wherein in a mode of operation a continuous, quasi-continuous or pulsed beam of ions is orthogonally... |
US-9,412,574 |
Parallel elemental and molecular mass spectrometry analysis with laser
ablation sampling An apparatus for mass spectrometry includes a laser ablation sampler comprising a laser ablation chamber and a laser which produces a laser beam. The laser... |
US-9,412,573 |
Method and apparatus for extraction, detection, and characterization of
vapors from explosives, taggants in... An improved method of extraction, detection, and characterization of a vapor from an explosive, a taggant in an explosive, a controlled substance, a biohazard,... |
US-9,412,572 |
Sample holders and methods of using them Certain embodiments described herein are directed to sample holders that can be used to retain a sample support effective for use in direct sample analysis. In... |
US-9,412,571 |
Imaging mass spectrometric data processing method and imaging mass
spectrometer Compressed data of mass spectra obtained at respective measurement points and normalization coefficients for XIC normalization or the like are stored in a... |
US-9,412,570 |
Mass spectrometer A hardware module which operatively carries out a method of compressing mass spectral data, the method comprising: receiving a first signal output from an ion... |
US-9,412,569 |
Remote arc discharge plasma assisted processes A coating system includes a vacuum chamber and a coating assembly positioned within the vacuum chamber. The coating assembly includes a vapor source that... |
US-9,412,568 |
Large-area sputtering targets In various embodiments, joined sputtering targets are formed at least in part by spray deposition of the sputtering material and/or welding. |
US-9,412,567 |
Plasma monitoring method and plasma monitoring system A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the... |
US-9,412,566 |
Methods and apparatus for depositing and/or etching material on a
substrate Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a... |
US-9,412,565 |
Temperature measuring method and plasma processing system A temperature measuring method for measuring a temperature of a member corresponding to a measuring object arranged within a chamber of a plasma processing... |