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Patent # Description
US-9,412,463 Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines
Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down...
US-9,412,462 3D stacked memory array and method for determining threshold voltages of string selection transistors
This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by...
US-9,412,461 Nonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device includes: a first memory cell transistor; a first bit line; a first sense amplifier unit;...
US-9,412,460 Plural operation of memory device
An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on...
US-9,412,459 Semiconductor device
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section...
US-9,412,458 Semiconductor memory device
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A...
US-9,412,457 Semiconductor memory apparatus, data transmission device, and recording method
According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying...
US-9,412,456 Nonvolatile memory device, programming method of nonvolatile memory device and memory system including...
Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory...
US-9,412,455 Data write control device and data storage device
According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment...
US-9,412,454 Semiconductor memory device and method for driving the same
According to one embodiment, a semiconductor memory device includes: semiconductor member; electrode member; charge accumulation member; a memory unit; and a...
US-9,412,453 Memory system and method of determining a failure in the memory system
An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating...
US-9,412,452 Semiconductor device
A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed...
US-9,412,451 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A...
US-9,412,450 Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory
Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a...
US-9,412,449 Semiconductor storage device
A semiconductor storage device according to an embodiment comprises a plurality of column power supply lines and a plurality of row power supply lines. A...
US-9,412,448 C-element with non-volatile back-up
The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between...
US-9,412,447 DDR compatible memory circuit architecture for resistive change element arrays
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and...
US-9,412,446 Multilevel resistive information storage and retrieval
The present invention relates to resistive random-access memory (RRAM or ReRAM) systems, as well as methods of employing multiple state variables to form...
US-9,412,445 Resistive memory apparatus and reading method thereof
A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a...
US-9,412,444 Electronic device
An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among...
US-9,412,443 Processor system having variable capacity memory
According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the...
US-9,412,442 Methods for forming a nanowire and apparatus thereof
A system that incorporates teachings of the subject disclosure may include, for example, a method for depositing a first material that substantially covers a...
US-9,412,441 Semiconductor memory device
A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a...
US-9,412,440 Systems and methods of pipelined output latching involving synchronous memory arrays
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is...
US-9,412,439 Hybrid TFET-MOSFET circuit design
A circuit includes a hybrid switch, which includes a Tunnel Field-Effect Transistor (TFET) having a first source, a first drain, and a first gate. The hybrid...
US-9,412,438 Writing data to a memory cell
A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A...
US-9,412,437 SRAM with buffered-read bit cells and its testing
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a...
US-9,412,436 Memory elements with soft error upset immunity
Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes....
US-9,412,435 Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time
A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals,...
US-9,412,434 Semiconductor device and semiconductor system for performing an initialization operation
Semiconductor systems are provided. A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor...
US-9,412,433 Counter based design for temperature controlled refresh
A DRAM includes: a temperature sensor for monitoring a temperature operating condition of the DRAM; and a binary counter coupled to the temperature sensor, for...
US-9,412,432 Semiconductor storage device and system provided with same
A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another;...
US-9,412,431 Semiconductor memory device and memory system including the same
A semiconductor memory device includes: a command generator suitable for generating an internal active command signal corresponding to an active command signal,...
US-9,412,430 Electronic device and method for fabricating the same
An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first...
US-9,412,429 Memory device with multiple voltage generators
A semiconductor memory device includes multiple voltage generators. The memory device includes a first voltage generator for generating a first internal voltage...
US-9,412,428 Memory components and controllers that calibrate multiphase synchronous timing references
A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a...
US-9,412,427 Precharge circuit and semiconductor apparatus including the same
A semiconductor apparatus includes a memory region configured to store data transmitted through a first data line and a second data line; and a precharge block...
US-9,412,426 Electronic apparatus and method for memory control
An electronic apparatus having plural memories of different performances such as bus widths facilitates achievement of its potential as a system. The electronic...
US-9,412,425 Device and method for improving reading speed of memory
A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of...
US-9,412,424 Noise tolerant sense circuit
A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling...
US-9,412,423 Memory modules including plural memory devices arranged in rows and module resistor units
A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA...
US-9,412,422 Memory device and method for putting a memory cell into a state with a reduced leakage current consumption
In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The...
US-9,412,421 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-9,412,420 Hermetically sealing a disk drive assembly
A method for forming a seal for hermetically sealing a hard disk drive assembly. The method includes forming a solder channel within a top cover of a disk drive...
US-9,412,419 Hard disk drive module
A hard disk drive (HDD) module includes two cartridges for receiving two HDDs. Each cartridge includes a bottom tray and a top cover adjustably connected to the...
US-9,412,418 In-box quick release access device structure
An in-box quick release access device mounting structure includes a rigid holder shell including an accommodation chamber surrounded by a bottom panel and two...
US-9,412,417 Persistent group of media items for a media device
Improved techniques to utilize and manage a group of media items (or media assets) on a computing device are disclosed. The group of media items can be utilized...
US-9,412,416 Location-based media presentation
Media can be presented based on location associated with presentation of media (e.g., physical location of a device that is to present media). Presentation of...
US-9,412,415 Content synchronization system, content-synchronization control device, and content playback device
When long polling is employed under HTTP, a content-synchronization control device can control each content playback device so that content control is...
US-9,412,414 Spatial conform operation for a media-editing application
Some embodiments provide a method that receives the addition of a video clip having a first set of spatial properties to a composite video project having a...
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