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Method and system for platform management messages across peripheral
component interconnect express (PCIe) segments
A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root...
Platform neutral device protocols
Platform neutral device protocol techniques are described in which functionality to customize device interactions through communication busses is made...
System and method for a thin-client terminal system with a local screen
buffer using a serial bus
In a system and method for a thin-client terminal system having a local screen buffer using a serial bus, a serial bus interface device receives encoded data...
Coupling a specialty system, such as metering system, to multiple control
A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing...
A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus...
The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part,...
Function approximation circuitry
Function approximation circuitry approximates an arbitrary function F over discrete inputs. Discrete values of the function F are stored in a lookup table (LUT)...
Software debouncing and noise filtering modules for interrupts
Systems and methods for debouncing a signal line within a computer device are provided. The mechanical nature of physical buttons and switches oftentimes...
Dynamic frequency memory control
A memory controller (40) is adaptable to scaling of a system clock frequency, to enable another device (10) to access a memory (20), and has a part for...
Systems and methods for dynamically determining a priority for a queue of
System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received...
Conversion device, peripheral device and programmable logic controller
An A/D conversion device includes an input-data storage unit storing therein a plurality of digital values obtained after A/D conversion so that each of the...
Key formation techniques are described. In one or more implementations, an input device includes a key assembly including a plurality of keys that are usable to...
Efficient calibration of a low power parallel data communications channel
A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined...
Chunk-level client side encryption in hierarchical content addressable
Techniques for chunk-level client side encryption are provided. In a content-addressable storage system, a plurality of chunks is used to implement a...
Secure replay protected storage
Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such...
Dynamic subroutine stack protection
A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack...
Computer system, computer and method for performing thin provisioning
capacity management in coordination with...
In the computer system, a storage system provides a storage level virtual volume based on thin provisioning technology, to a physical server on which a virtual...
Multi-core heterogeneous system translation lookaside buffer coherency
Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with...
Content-based caching in a managed runtime computing environment
A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source...
Detecting memory corruption
A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an...
Use of differing granularity heat maps for caching and migration
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and...
System and method for application level caching
The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a...
Electronic device including a semiconductor memory
This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the...
System, method and apparatus for improving transactional memory (TM)
throughput using TM region indicators
Systems, apparatuses, and methods for improving transactional memory (TM) throughput using a TM region indicator (or color) are described. Through the use of TM...
Efficient processing of cache segment waiters
Various embodiments for cache management in a distributed computing storage environment are provided. In one embodiment, a processor device, for a plurality of...
Clearing blocks of storage class memory
An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard...
System and method for an accelerator cache based on memory availability
The storage processor of a data storage system such as a storage array automatically configures one or more accelerator caches ("AC") upon detecting the...
Counter-based wide fetch management
Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to...
Electronic devices having semiconductor memory units and method of
fabricating the same
Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor...
Sharing pattern-based directory coherence for multicore scalability
A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term...
Push-based cache invalidation notification
In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data...
System and method for managing transactions
A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a...
Private memory table for reduced memory coherence traffic
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor...
Salvaging lock elision transactions
A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about...
Methods and apparatus for efficient communication between caches in
hierarchical caching design
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient...
Split write operation for resistive memory cache
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write...
Low power computation architecture
An embodiment includes a system, comprising a first memory; a plurality of first circuits, wherein each first circuit is coupled to the memory; and includes a...
Application-reserved cache for direct I/O
Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache...
Method and apparatus for a partial-address select-signal generator with
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a...
Data exchange system
A data exchange system including: a microprocessor; a non-volatile memory; a first communication channel linking the microprocessor to the non-volatile memory;...
Asynchronous FIFO buffer for memory access
An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data...
Detecting access sequences for data compression on non-volatile memory
Techniques are presented to allow non-volatile memory system to operate by determining ranges of logical addresses that a host typically accesses as together....
Information processing apparatus equipped with overwrite deletion
function, method of controlling the same, and...
An information processing apparatus which is capable of effectively using an overwrite deletion function and a hibernation function. An image forming apparatus...
Memory system including nonvolatile and volatile memory and operating
A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory...
Method to apply fine grain wear leveling and garbage collection
An apparatus includes a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) measure a rate of free...
Metadata journaling with error correction redundancy
Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata...
System and method for controlling automated page-based tier management in
System and method for automated page-based management in storage systems. The system includes host computers, file servers and a storage system having automated...
System, method, and computer program product for optimizing the management
of thread stack memory
A system, method, and computer program product for optimizing thread stack memory allocation is disclosed. The method includes the steps of receiving source...
Finite state machine for system management
Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic....
Method for supporting product design and product design support apparatus
A computer refers to a first document, second documents related to the first document, test documents related to the respective second documents, and test...