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Patent # Description
US-9,419,119 Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor...
US-9,419,118 Trench IGBT with tub-shaped floating P-well and hole drains to P-body regions
A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has...
US-9,419,117 Semiconductor device, and manufacturing method for same
The present invention is directed to a semiconductor device including a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first...
US-9,419,116 Diodes and methods of manufacturing diodes
Diodes and methods of manufacturing diodes are disclosed. In some examples, the diodes may include a cathode assembly. The cathode assembly may include a...
US-9,419,115 Junctionless tunnel fet with metal-insulator transition material
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially...
US-9,419,114 Tunnel field-effect transistor
A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure...
US-9,419,113 Semiconductor device and manufacturing method thereof
An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source...
US-9,419,112 Method for manufacturing fin structure
A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a...
US-9,419,111 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related...
A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the...
US-9,419,110 Method for reducing contact resistance in MOS
A method for growing a III-V semiconductor structure on a Si.sub.nGe.sub.1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of:...
US-9,419,109 Semiconductor device and method for fabricating the same
A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the...
US-9,419,108 Semiconductor structure and method for manufacturing the same
One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor...
US-9,419,107 Method for fabricating vertically stacked nanowires for semiconductor applications
Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field...
US-9,419,106 Non-planar transistors and methods of fabrication thereof
The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar...
US-9,419,105 Method for processing substrate and method for fabricating apparatus
A method for processing a substrate, the substrate comprising an organic film pattern, the method comprising: a fusion/deformation step of fusing said organic...
US-9,419,104 Semiconductor device and method of manufacturing the same
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate,...
US-9,419,103 Stress modulation in field effect transistors in reducing contact resistance and increasing charge carrier mobility
Field-effect transistor and method of fabrication are provided for, for instance, providing a gate structure disposed over a substrate. The fabricating method...
US-9,419,102 Method to reduce parasitic gate capacitance and structure for same
Disclosed are methods of forming a semiconductor structure comprising forming, on a supporting substrate, a plurality of composite structures, each comprising...
US-9,419,101 Multi-layer spacer used in finFET
A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate;...
US-9,419,100 Method for fabricating a metal gate electrode
Exemplary methods for fabricating a metal gate electrode include forming a dielectric layer on a substrate, and forming a first trench having a first width and...
US-9,419,099 Method of fabricating spacers in a strained semiconductor device
The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy...
US-9,419,098 Tuning strain in semiconductor devices
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first...
US-9,419,097 Replacement metal gate dielectric cap
A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method...
US-9,419,096 Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy...
A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a...
US-9,419,095 Method for manufacturing dummy gate in gate-last process and dummy gate in gate-last process
A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a...
US-9,419,094 Semiconductor device including a gate electrode on a protruding group III-V material layer and method of...
A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate,...
US-9,419,093 Method of forming a high electron mobility transistor
A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source...
US-9,419,092 Termination for SiC trench devices
A silicon carbide device has a termination region that includes a mesa region that links the termination region to an active area of the device and that...
US-9,419,091 Trenched gate with sidewall airgap spacer
A method for fabricating a semiconductor device may include receiving a device substrate comprising a channel layer and a source or drain layer, forming a gate...
US-9,419,090 Interconnect structures and fabrication method thereof
An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact...
US-9,419,089 Semiconductor structure and manufacturing method thereof
The present invention provides a semiconductor structure, which includes a substrate, at least two gate structures disposed on the substrate, a first recess,...
US-9,419,088 Low resistance polysilicon strap
A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall...
US-9,419,087 Bipolar junction transistor formed on fin structures
A Bipolar Junction Transistor (BJT) includes an elongated collector line, an elongated emitter line parallel to the collector line, and an elongated base line...
US-9,419,086 Recessed contact to semiconductor nanowires
A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds...
US-9,419,085 Lateral devices containing permanent charge
A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and...
US-9,419,084 Devices, components and methods combining trench field plates with immobile electrostatic charge
N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the...
US-9,419,083 Semiconductor structures having a gate field plate and methods for forming such structure
A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region...
US-9,419,082 Source/drain profile engineering for enhanced p-MOSFET
P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are...
US-9,419,081 Reusable substrate bases, semiconductor devices using such reusable substrate bases, and methods for making the...
Reusable substrate bases for producing multilayer semiconductor devices are provided, as well as free-standing semiconductor devices and reusable substrate...
US-9,419,080 Semiconductor device with recombination region
A semiconductor device includes a pn junction between a drift zone and a charge-carrier transfer region in a semiconductor body. An access channel provides a...
US-9,419,079 Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with...
A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit...
US-9,419,078 Floating body memory with asymmetric channel
A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material. The fin has a first side surface...
US-9,419,077 Semiconductor devices including protruding insulation portions between active fins
A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a...
US-9,419,076 Bipolar junction transistor
A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower...
US-9,419,075 Wafer substrate removal
A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is...
US-9,419,074 Non-planar semiconductor device with aspect ratio trapping
As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk...
US-9,419,073 Integrated RF front end system
Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band...
US-9,419,072 Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern...
US-9,419,071 Integrated circuit comprising at least an integrated antenna
An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line...
US-9,419,070 Composite reconstituted wafer structures
A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the...
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