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Patent # Description
US-9,419,019 Array substrate and display device
An array substrate and a display device is disclosed, for eliminating the interference of transient electromagnetic signals caused by the time-varying voltages...
US-9,419,018 Semiconductor device and method for manufacturing the same
A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer,...
US-9,419,017 Active matrix substrate, display device, and short circuit defect correction method for active matrix substrate
A slit-shaped repair hole (27S) for repairing a short circuit defect of adjacent pixel electrodes (27) is provided straddling a storage capacitance wiring line...
US-9,419,016 Junctionless tunnel FET with metal-insulator transition material
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially...
US-9,419,015 Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device
Methods for integrating core and I/O components in IC devices utilizing a TFT I/O device formed on STI regions, and the resulting devices are disclosed....
US-9,419,014 Alternating tap-cell strategy in a standard cell logic block for area reduction
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a...
US-9,419,013 Semiconductor device and method of manufacturing the same
A semiconductor device, including gate electrodes perpendicularly stacked on a substrate; channel holes extending perpendicularly to the substrate, the channel...
US-9,419,012 Three-dimensional memory structure employing air gap isolation
Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling...
US-9,419,011 Three-dimensional semiconductor devices
Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an...
US-9,419,010 High aspect ratio etching method
A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer...
US-9,419,009 3D nonvolatile memory device
A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein...
US-9,419,008 Method of fabricating semiconductor devices having vertical cells
According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower...
US-9,419,007 Semiconductor device
A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a...
US-9,419,006 Process for 3D NAND memory with socketed floating gate cells
A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different...
US-9,419,005 Semiconductor device, related manufacturing method, and related electronic device
A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a...
US-9,419,004 Fuse structure and semiconductor device including the same
A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the...
US-9,419,003 Semiconductor devices and methods of manufacture thereof
An SRAM cell includes a first vertical pull-up transistor stacked atop a first vertical pull-down transistor, and a second vertical pull-up transistor stacked...
US-9,419,002 Semiconductor device for reducing coupling capacitance
A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line...
US-9,419,001 Method for forming cell contact
A method for forming a cell contact. A substrate having first and second protruding structures is prepared. An etch stop layer is deposited over the substrate....
US-9,419,000 Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove...
US-9,418,999 MIM capacitors with improved reliability
A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing...
US-9,418,998 Semiconductor devices including a bit line structure and a contact plug
Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit...
US-9,418,997 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-9,418,996 Method of manufacturing semiconductor integrated circuit device
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain...
US-9,418,995 Method and structure for transistors using gate stack dopants with minimal nitrogen penetration
Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is...
US-9,418,994 Fin field effect transistor (FinFET) device structure
A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate, and the substrate includes a first...
US-9,418,993 Device and method for a LDMOS design for a FinFET integrated circuit
Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well...
US-9,418,992 High performance power cell for RF power amplifier
A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well...
US-9,418,991 ROM chip manufacturing structures
An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include...
US-9,418,990 Semiconductor device and method of manufacturing the same
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from...
US-9,418,989 Semiconductor device and display device
A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second...
US-9,418,988 Gate electrode and gate contact plug layouts for integrated circuit field effect transistors
A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions....
US-9,418,987 Transistor with threshold voltage set notch and method of fabrication thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced .sigma.V.sub.T...
US-9,418,986 Semiconductor device
A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is...
US-9,418,985 Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit...
US-9,418,984 Normally off power electronic component
An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the...
US-9,418,983 Semiconductor device and associated method for manufacturing
A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a...
US-9,418,982 Multi-layered integrated circuit with selective temperature coefficient of resistance
The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second...
US-9,418,981 High-voltage electrostatic discharge device incorporating a metal-on-semiconductor and bipolar junction structure
A semiconductor device formed in a substrate, including a first region, a second region formed over the first region, a third region, a fourth region formed...
US-9,418,980 Light-emitting diode device
A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the...
US-9,418,979 Light emitting diodes and a method of packaging the same
Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies...
US-9,418,978 Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching...
A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material....
US-9,418,977 Package-on-package semiconductor device
Exemplary methods of forming the semiconductor device, encompasses forming a first package with at least one first die on a packaging substrate that is...
US-9,418,976 Chip stack with electrically insulating walls
A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically...
US-9,418,975 Semiconductor module, power conversion device, and method for manufacturing semiconductor module
A semiconductor module has a first electrode terminal, a second electrode terminal, a third electrode terminal, a fourth electrode terminal, a fifth electrode...
US-9,418,974 Stacked semiconductor die assemblies with support members and associated systems and methods
Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,418,973 Light emitting device package
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and...
US-9,418,972 Optoelectronic component with protective circuit
An optoelectronic component includes at least one first carrier with at least two light emitting diodes, wherein each diode has two electrical connections, each...
US-9,418,971 Package-on-package structure including a thermal isolation material and method of forming the same
A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first...
US-9,418,970 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
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