Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,418,969 Packaged semiconductor devices and packaging methods
Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and...
US-9,418,968 Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
US-9,418,967 Semiconductor device
A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first...
US-9,418,966 Semiconductor assembly having bridge module for die-to-die interconnection
In one example, a semiconductor assembly comprises a first IC die, a second IC die, and a bridge module. The first IC die includes, on a top side thereof, first...
US-9,418,965 Embedded interposer with through-hole vias
A method of forming an integrated circuit package may include forming a first layer of a package substrate and mounting an interposer structure on the first...
US-9,418,964 Chip package structure
A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips...
US-9,418,963 Methods for wafer bonding, and for nucleating bonding nanophases
Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second...
US-9,418,962 Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant...
A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die...
US-9,418,961 Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects
An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that...
US-9,418,960 Semiconductor chip and semiconductor package
The driver semiconductor package includes a base substrate. The semiconductor package includes a semiconductor chip mounted on the base substrate. The...
US-9,418,959 Systems of bonded substrates
A system of bonded substrates may include a first substrate, a second substrate, and a composite bonding layer. The first substrate may include a bonding...
US-9,418,958 Anisotropic conductive adhesive
An anisotropic conductive adhesive includes an epoxy adhesive containing an epoxy compound and a curing agent and conducive particles dispersed in the epoxy...
US-9,418,957 Semiconductor package, printed circuit board substrate and semiconductor device
A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer...
US-9,418,956 Zero stand-off bonding system and method
A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a...
US-9,418,955 Plasma treatment for semiconductor devices
A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer...
US-9,418,954 Integrated circuit chip assembled on an interposer
A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal...
US-9,418,953 Packaging through pre-formed metal pins
A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the...
US-9,418,952 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
US-9,418,951 Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof
A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate...
US-9,418,950 Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power...
An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and...
US-9,418,949 Semiconductor device having voids between top metal layers of metal interconnects
The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal...
US-9,418,948 Method of making bond pad
A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at...
US-9,418,947 Mechanisms for forming connectors with a molding compound for package on package
The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package...
US-9,418,945 Integrated circuit for generating or processing a radio frequency signal
An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an...
US-9,418,944 Semiconductor package
A semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device...
US-9,418,943 Semiconductor package and method of manufacturing the same
A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may...
US-9,418,942 Semiconductor device
In one embodiment, a semiconductor package includes a first semiconductor die having a first surface facing upwardly to expose a bond pad, a second ...
US-9,418,941 Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in...
A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage...
US-9,418,940 Structures and methods for stack type semiconductor packaging
Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted...
US-9,418,939 Contact structure for NAND based non-volatile memory device and a method of manufacture
A NAND-based non-volatile memory contact structure includes a trench located adjacent to layered alternating conducting and insulating layers, the layers lining...
US-9,418,938 Semiconductor device having a graphene interconnect
A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via...
US-9,418,937 Integrated circuit and method of forming an integrated circuit
An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 .mu.m and a ratio...
US-9,418,936 Power line structure for semiconductor apparatus
A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of...
US-9,418,935 Integrated circuit line ends formed using additive processing
Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first...
US-9,418,934 Structure and fabrication method for electromigration immortal nanoscale interconnects
After forming a trench opening including narrow trench portions spaced apart by wide trench portions and forming a stack of a first diffusion barrier layer and...
US-9,418,933 Through-substrate via formation with improved topography control
A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first...
US-9,418,932 Integrated circuit system with tunable resistor and method of manufacture thereof
An integrated circuit system, and a method of manufacture thereof, includes: an integrated circuit substrate; and a discretized tunable precision resistor...
US-9,418,931 Package structure and manufacturing method thereof
A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is...
US-9,418,930 Power module
A power module, having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer, the core being...
US-9,418,929 Integrated circuit with sewn interconnects
A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to...
US-9,418,928 Protrusion bump pads for bond-on-trace processing
An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion...
US-9,418,927 Stretchable electronic device
A stretchable electronic device is disclosed. In one aspect, the device includes at least one combination of a stretchable electronic structure having a first...
US-9,418,926 Package-on-package semiconductor assemblies and methods of manufacturing the same
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
US-9,418,925 Electronic component and method for electrically coupling a semiconductor die to a contact pad
In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode...
US-9,418,924 Stacked die integrated circuit
An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending...
US-9,418,923 Semiconductor component having through-silicon vias and method of manufacture
A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the...
US-9,418,922 Semiconductor device with reduced thickness
A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy...
US-9,418,921 Power module
A power module includes a first substrate, at least two power elements, at least one first conductive structure and at least one leadframe. The first substrate...
US-9,418,920 Integrated circuit (IC) package with thick die pad functioning as a heat sink
An integrated circuit (IC) package includes a die pad and an IC die secured on the die pad. The IC die had outer edges aligned with outer edges of the die pad....
US-9,418,919 Leadless chip carrier having improved mountability
Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.