Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,418,918 Lead for connection to a semiconductor device
There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having...
US-9,418,916 Semiconductor device
A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first...
US-9,418,915 Semiconductor device and method for fabricating the same
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating...
US-9,418,914 Package substrates, semiconductor packages having the package substrates
Package substrates, semiconductor packages including the package substrates, and methods for fabricating the semiconductor packages are provided. A package...
US-9,418,913 Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in...
A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive...
US-9,418,912 Methods of forming serpentine thermal interface material and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal...
US-9,418,911 Three-dimensional semiconductor memory device having sidewall and interlayer molds
Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold...
US-9,418,910 Semiconductor device
A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are...
US-9,418,909 Stacked silicon package assembly having enhanced lid adhesion
A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is...
US-9,418,908 Wafer processing method
A wafer processing method includes a first correction step of measuring a distance "a" between a first cut groove previously formed by a first cutting unit and...
US-9,418,907 Method for manufacturing semiconductor device
A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on the...
US-9,418,906 Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at...
US-9,418,905 Adaptive patterning for panelized packaging
An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or...
US-9,418,904 Localized CMP to improve wafer planarization
To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This...
US-9,418,903 Structure and method for effective device width adjustment in finFET devices using gate workfunction shift
Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction...
US-9,418,902 Forming isolated fins from a substrate
A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a...
US-9,418,901 Semiconductor device containing HEMT and MISFET and method of forming the same
A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V...
US-9,418,900 Silicon germanium and silicon fins on oxide from bulk wafer
A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon...
US-9,418,899 Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and...
A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG...
US-9,418,898 Integrated circuits with selective gate electrode recess
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
US-9,418,897 Wrap around silicide for FinFETs
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the...
US-9,418,896 Semiconductor device and fabricating method thereof
Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first...
US-9,418,895 Dies for RFID devices and sensor applications
Deep reactive ion silicon etching of a device wafer, laser-induced release of individual dies, and individual placement of the dies on flexible substrates...
US-9,418,894 Electronic die singulation method
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier...
US-9,418,893 Organic electroluminescent device and method for fabricating the same
Disclosed an organic electroluminescent device and a method for fabricating the same. The device may include a thin film transistor disposed on a substrate; a...
US-9,418,892 Transistor, semiconductor device and method of manufacturing the same
A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier...
US-9,418,891 Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and...
A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer;...
US-9,418,890 Method for tuning a deposition rate during an atomic layer deposition process
Embodiments of the invention provide methods for depositing a material on a substrate within a processing chamber during a vapor deposition process, such as an...
US-9,418,889 Selective formation of dielectric barriers for metal interconnects in semiconductor devices
A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric,...
US-9,418,888 Non-lithographically patterned directed self assembly alignment promotion layers
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
US-9,418,887 Method of manufacturing semiconductor device
According to one embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first insulating film, forming a first...
US-9,418,886 Method of forming conductive features
A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive...
US-9,418,885 Semiconductor manufacturing apparatus
Disclosed is a semiconductor manufacturing apparatus including at least one pocket on which a passive subject on which deposition will be executed is mounted,...
US-9,418,884 Electrostatic chuck and semiconductor manufacturing device
An electrostatic chuck includes a placing stage formed from a ceramic including aluminum oxide and yttrium oxide, and an electrostatic electrode arranged in the...
US-9,418,883 Device for holding wafer shaped articles
A device for holding a wafer-shaped article comprises an annular chuck base body having a plurality of movable contact elements for securing a wafer-shaped...
US-9,418,882 Device and method for aligning substrates
A method for alignment and contact-making of a first substrate with a second substrate using several detection units as well as a corresponding device.
US-9,418,881 Substrate processing apparatus capable of switching control mode of heater
Provided is a substrate processing apparatus capable of suppressing inferiority when heat treatment is controlled using a temperature sensor. The substrate...
US-9,418,880 Apparatuses and methods for treating substrate
Provided is a substrate treating apparatus, which includes a process chamber providing a space in which a substrate is treated, an exhausting pipe connected to...
US-9,418,879 Low cost interposer and method of fabrication
A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer...
US-9,418,878 Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in WLCSP
A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An...
US-9,418,877 Integrated device comprising high density interconnects in inorganic layers and redistribution layers in...
Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first...
US-9,418,876 Method of three dimensional integrated circuit assembly
A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of...
US-9,418,875 Substrate including a dam for semiconductor package, semiconductor package using the same, and manufacturing...
A substrate for a semiconductor package includes a substrate body having a first surface and a second surface which faces away from the first surface, and...
US-9,418,874 Method of fabricating semiconductor package
A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for...
US-9,418,873 Integrated circuit with on-die decoupling capacitors
A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the...
US-9,418,872 Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
US-9,418,871 Systems and methods for annealing semiconductor structures
Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure...
US-9,418,870 Silicon germanium-on-insulator formation by thermal mixing
A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal...
US-9,418,869 Method to etch a tungsten containing layer
A method for etching a tungsten containing layer is provided. An etch gas is provided comprising O.sub.2 and a fluorine containing component, wherein the etch...
US-9,418,868 Method of fabricating semiconductor device with reduced trench distortions
A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.