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Lead for connection to a semiconductor device
There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having...
A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first...
Semiconductor device and method for fabricating the same
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating...
Package substrates, semiconductor packages having the package substrates
Package substrates, semiconductor packages including the package substrates, and methods for fabricating the semiconductor packages are provided. A package...
Semiconductor device and method of forming insulating layer on conductive
traces for electrical isolation in...
A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive...
Methods of forming serpentine thermal interface material and structures
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal...
Three-dimensional semiconductor memory device having sidewall and
Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold...
A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are...
Stacked silicon package assembly having enhanced lid adhesion
A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is...
Wafer processing method
A wafer processing method includes a first correction step of measuring a distance "a" between a first cut groove previously formed by a first cutting unit and...
Method for manufacturing semiconductor device
A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on the...
Space and cost efficient incorporation of specialized input-output pins on
integrated circuit substrates
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at...
Adaptive patterning for panelized packaging
An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or...
Localized CMP to improve wafer planarization
To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This...
Structure and method for effective device width adjustment in finFET
devices using gate workfunction shift
Embodiments of the present invention provide methods and structures by which the inherent discretization of effective width can be relaxed through introduction...
Forming isolated fins from a substrate
A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a...
Semiconductor device containing HEMT and MISFET and method of forming the
A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V...
Silicon germanium and silicon fins on oxide from bulk wafer
A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon...
Method of multi-WF for multi-Vt and thin sidewall deposition by
implantation for gate-last planar CMOS and...
A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG...
Integrated circuits with selective gate electrode recess
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
Wrap around silicide for FinFETs
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the...
Semiconductor device and fabricating method thereof
Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first...
Dies for RFID devices and sensor applications
Deep reactive ion silicon etching of a device wafer, laser-induced release of individual dies, and individual placement of the dies on flexible substrates...
Electronic die singulation method
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier...
Organic electroluminescent device and method for fabricating the same
Disclosed an organic electroluminescent device and a method for fabricating the same. The device may include a thin film transistor disposed on a substrate; a...
Transistor, semiconductor device and method of manufacturing the same
A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier...
Method for fabricating semiconductor device including silicon-containing
layer and metal-containing layer, and...
A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer;...
Method for tuning a deposition rate during an atomic layer deposition
Embodiments of the invention provide methods for depositing a material on a substrate within a processing chamber during a vapor deposition process, such as an...
Selective formation of dielectric barriers for metal interconnects in
A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric,...
Non-lithographically patterned directed self assembly alignment promotion
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
Method of manufacturing semiconductor device
According to one embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first insulating film, forming a first...
Method of forming conductive features
A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive...
Semiconductor manufacturing apparatus
Disclosed is a semiconductor manufacturing apparatus including at least one pocket on which a passive subject on which deposition will be executed is mounted,...
Electrostatic chuck and semiconductor manufacturing device
An electrostatic chuck includes a placing stage formed from a ceramic including aluminum oxide and yttrium oxide, and an electrostatic electrode arranged in the...
Device for holding wafer shaped articles
A device for holding a wafer-shaped article comprises an annular chuck base body having a plurality of movable contact elements for securing a wafer-shaped...
Device and method for aligning substrates
A method for alignment and contact-making of a first substrate with a second substrate using several detection units as well as a corresponding device.
Substrate processing apparatus capable of switching control mode of heater
Provided is a substrate processing apparatus capable of suppressing inferiority when heat treatment is controlled using a temperature sensor. The substrate...
Apparatuses and methods for treating substrate
Provided is a substrate treating apparatus, which includes a process chamber providing a space in which a substrate is treated, an exhausting pipe connected to...
Low cost interposer and method of fabrication
A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer...
Semiconductor device and method of forming adhesive material to secure
semiconductor die to carrier in WLCSP
A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An...
Integrated device comprising high density interconnects in inorganic
layers and redistribution layers in...
Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first...
Method of three dimensional integrated circuit assembly
A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of...
Substrate including a dam for semiconductor package, semiconductor package
using the same, and manufacturing...
A substrate for a semiconductor package includes a substrate body having a first surface and a second surface which faces away from the first surface, and...
Method of fabricating semiconductor package
A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for...
Integrated circuit with on-die decoupling capacitors
A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the...
Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
Systems and methods for annealing semiconductor structures
Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure...
Silicon germanium-on-insulator formation by thermal mixing
A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal...
Method to etch a tungsten containing layer
A method for etching a tungsten containing layer is provided. An etch gas is provided comprising O.sub.2 and a fluorine containing component, wherein the etch...
Method of fabricating semiconductor device with reduced trench distortions
A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first...