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Patent # Description
US-9,418,766 Fuel assembly for a boiling water reactor
A fuel assembly of a boiling water reactor contains a fuel assembly base closed at the top by a filter plate, a fuel assembly head, and, disposed between them,...
US-9,418,765 Nuclear reactor cores comprising a plurality of fuel elements, and fuel elements for use therein
In a nuclear reactor core, each of a plurality of pressure tubes contains fuel elements spaced apart to permit coolant to flow through spaces between adjacent...
US-9,418,764 Actuator device and process for producing an actuator device
Actuator device having an expansion unit, which includes a magnetic shape memory alloy material, and a spring unit which interacts therewith in a restoring...
US-9,418,763 Memory array, memory device, and methods for reading and operating the same
The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of...
US-9,418,762 Semiconductor memory device
A semiconductor memory device may include: a first fuse set unit suitable for storing a first repair address during a first mode; a second fuse set unit...
US-9,418,761 Apparatus for boosting source-line voltage to reduce leakage in resistive memories
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a...
US-9,418,760 Integrated circuit and method for testing semiconductor devices using the same
An integrated circuit includes first to third failure information storage units, an input selection unit suitable for alternately storing plural pieces of...
US-9,418,759 Assist circuits for SRAM testing
Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist...
US-9,418,758 Test circuit of semiconductor apparatus
A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks,...
US-9,418,757 Method for testing semiconductor apparatus and test system using the same
This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to...
US-9,418,756 Threshold voltage compensation circuit of thin film transistor and method for the same, shift register, and...
Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage...
US-9,418,755 Shift register and flat panel display device including the same
Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a...
US-9,418,754 Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays
An anti-fuse type OTP memory cell includes a first anti-fuse transistor having a first channel width, a first selection transistor sharing a first active region...
US-9,418,753 Method of operating memory controller and data storage device including memory controller
In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a...
US-9,418,752 Ramping inhibit voltage during memory programming
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit...
US-9,418,751 Pre-program detection of threshold voltages of select gate transistors in a memory device
A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate...
US-9,418,750 Single ended word line and bit line time constant measurement
In non-volatile memories, bit lines and word lines commonly to driving and decoding circuitry on a single end. Techniques are presented for determining the time...
US-9,418,749 Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to...
US-9,418,748 Semiconductor memory device and method of operating the same
A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory...
US-9,418,747 Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level...
A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines,...
US-9,418,746 Storage devices and methods of operating storage devices
A storage device includes a nonvolatile memory having a plurality of memory cells and a memory controller to control the nonvolatile memory. The operating...
US-9,418,745 Rebalancing in twin cell memory schemes to enable multiple writes
A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read...
US-9,418,744 System and method to reduce disturbances during programming of flash memory cells
An improved control gate decoding design may reduce disturbances during the programming of flash memory cells. In one embodiment, a control gate line decoder is...
US-9,418,743 3D NAND memory with decoder and local word line drivers
A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of...
US-9,418,742 Nonvolatile semiconductor memory device and memory system having the same
A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information...
US-9,418,741 Content addressable memory with search line test circuitry
A content addressable memory (CAM) and methods of operating a CAM are provided. The method for operating a CAM includes: during a first mode, performing a...
US-9,418,740 Semiconductor storage device writing data into memory cells using a half selected state and a write state
A memory includes BLs and WLs. Resistance-change memory elements are connected between the BLs and the WLs via selection gates, respectively. A BL driver...
US-9,418,739 Memory devices and methods of operating the same
Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a...
US-9,418,738 Apparatuses and methods for efficient write in a cross-point array
A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and...
US-9,418,737 Nonvolatile semiconductor memory device and method of controlling the same
A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The...
US-9,418,736 High voltage generating circuit for resistive memory apparatus
A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a...
US-9,418,735 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,418,734 Multi-function resistance change memory cells and apparatuses including the same
Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory...
US-9,418,733 Joint short-time and long-time storage device and storage method thereof
A joint short-time and long-time storage device, including a first electrode layer, a functional material layer connected to the first electrode layer, and a...
US-9,418,732 Semiconductor memory device
A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected...
US-9,418,731 Memory management method, memory storage device and memory control circuit unit
A memory management method, a memory storage device and a memory control circuit unit are provided. The method comprises: obtaining a first threshold voltage...
US-9,418,730 Handshaking sense amplifier
Handshaking sense amplifier. In accordance with a first embodiment, an electronic circuit includes a sense amplifier configured to differentially sense contents...
US-9,418,729 Multi-port memory cell
A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a...
US-9,418,728 Dual-port static random-access memory cell
The present disclosure provides a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down...
US-9,418,727 Five transistor SRAM cell
A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The...
US-9,418,726 Data reception chip
A data reception chip coupled to an external memory including a first input-output pin to output first data and including a comparison module and a voltage...
US-9,418,725 Semiconductor device and method of driving the same
A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response...
US-9,418,724 Memory and memory system including the same
A memory includes a first cell array including a plurality of first memory cells connected to a plurality of word lines, a bit line selection unit configured to...
US-9,418,723 Techniques to reduce memory cell refreshes for a memory device
Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an...
US-9,418,722 Prioritizing refreshes in a memory device
A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory...
US-9,418,721 Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access...
Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include...
US-9,418,720 Pattern matching device
According to an embodiment, a pattern matching device includes unit cells, a circuit, and a measuring unit. Each unit cell includes a first magnetization...
US-9,418,719 In-memory computational device
A computing device comprising includes a memory array having a plurality of sections with memory cells arranged in rows and column, at least one cell in each...
US-9,418,718 Semiconductor apparatus with clock control
A semiconductor apparatus includes: a command control unit configured to decode external signals and generate a read strobe signal or a write strobe signal; a...
US-9,418,717 Tracking mechanism for writing to a memory cell
A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is...
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