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Wireless devices having reduced clock feed-through
Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced...
Inter carrier-aggregation isolation in a receiver
A device includes a first amplifier circuit coupled to a first transformer and a second transformer, the first transformer selectively coupled to a first shared...
An electronic device including a tunable antenna, a radio frequency (RF) signal transceiving module, a coupler and a control unit, is provided. The RF signal...
Error detection device and error detecting method
An error detection method includes: generating an input code sequence from a signal that repeatedly transmits a code sequence including data, an error detection...
Adaptive error correction codes (ECCs) for electronic memories
Systems and methods for adaptive error correction codes (ECCs) for electronic memories. In some embodiments, a memory device, may include a first memory having...
Memory device and memory system
A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit,...
DTV transmitting system and method of processing broadcast data
A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes...
Interleaver employing quotient-remainder reordering
A method of generating an interleaved symbol sequence location from a symbol location of a symbol sequence comprises determining the interleaved symbol location...
Path encoding and decoding
This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure...
Configurable multi-mode media independent interface
A configurable media independent interface in an integrated circuit device includes a first plurality of channels and a second plurality of channels, wherein...
State-split based encoder and decoder with table compression
A data encoder includes an encoding logic circuit configured to encode input data to apply run length limiting using state splitting of a code trellis, and a...
Simplified range and context update for multimedia context-adaptive binary
arithmetic coding design
In some aspects, the disclosure is directed to methods and systems for a context-adaptive binary arithmetic encoder and decoder utilizing a fixed point design...
Converting device and converting method
An information processing apparatus receives a compressed file in which character string data with a first character code is compressed by a unit of character...
Vector quantization with non-uniform distributions
Systems and methods are described for encoding quantized vector parameters in a bitstream are described. An exemplary method may include receiving a vector of...
Adaptive compression of data
A method of encoding data includes determining a magnitude of change between a first value associated with first data and a second value associated with second...
Noise shaping successive approximation register analog-to-digital
An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a...
High order correction for pulse width modulation (PWM) digital/analog
converters with reduced computation
A delta sigma modulator (DSM) may be improved by configuring it to set the high-order nonlinear function values to zero when the quantization value being output...
Generating comparator thresholds using a rotating ring of resistors
Data converters convert signals in analog form to digital form or from digital form to analog form. Due to mismatches between devices that are intended to be...
Hybrid pipelined analog-to-digital converter
An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register...
Redundancy scheme for flash assisted successive approximation register
(SAR) analog-to-digital converter (ADC)
Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and...
This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and...
Circuit calibrating method and circuit calibrating system
A circuit calibrating method, applied to an ACS generating circuit, which comprises a plurality of ACS generating units and activates the ACS generating unit...
Method and apparatus for compensating offset drift with temperature
The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is...
Frequency signal generating system and display device
A frequency signal generating system comprises a digital phase-locked loop for receiving a source frequency signal; a loop filter for filtering out high...
According to an embodiment, a local oscillator includes a digitally-controlled oscillator, a frequency multiplier, a phase data generator, a subtracter, a...
A frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second...
Circuit for symbol timing synchronization
The present disclosure relates to a timing synchronization circuit for a digital receiver structure that includes a timing error detection module comprising a...
Phase estimating device, signal generating device, synchronizing system,
and signal processing device
According to one embodiment, a phase estimating device includes a periodic signal obtaining unit that obtains a first periodic signal, and a wireless time...
Frequency dividing circuit and phase synchronization circuit
A frequency dividing circuit includes: a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output...
System and method for controlling superconducting quantum circuits using
single flux quantum logic circuits
A system and methods for controlling superconducting quantum circuits are provided. The system includes at least one superconducting quantum circuit described...
Apparatuses and methods for implementing various physically unclonable
function (PUF) and random number...
Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under...
Methods and apparatus for configuring and reconfiguring a partial
An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit...
Programmable logic circuit and nonvolatile FPGA
A programmable logic circuit according to an embodiment includes: a first programmable device with a first and second terminals, a resistance of the first...
Reconfigurable logic device
[Problem] To be able to provide a reconfigurable logic device having a small area and enhanced reprogramming characteristics. [Solution] A reconfigurable logic...
Reconfigurable logic gates using chaotic dynamics
The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least...
Reconfigurable semiconductor device
A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each...
High performance reconfigurable voltage buffers
In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high...
Data converting device, digital transmitting apparatus using the data
converting device, and related data...
A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal;...
Circuit and method for detection and compensation of transistor mismatch
The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator...
Testing system for power delivery network
Systems and apparatus for an integrated test tool for that utilizes reconfigurable hardware to assess power delivery quality. In one aspect, a method includes...
Circuit for generating bias voltage for high speed input/output pad
The present invention provides a circuit for generating a bias voltage for a high speed input/output pad. To this end, a bias voltage generator according to an...
Reconfigurable power switch chains for efficient dynamic power saving
Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for...
Semiconductor integrated circuit with shutoff control for plural power
A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control...
A conductive element which can serve as capacitive sensing element comprises a conductive pad comprising relatively low conductivity material, such as...
Reference voltage circuit and electronic device
Provided is a reference voltage circuit capable of forming optimal circuits for various modes of an electronic device. The reference voltage circuit includes,...
Current sensors and methods of improving accuracy thereof
A method for operating a circuit includes providing a three terminal main transistor and a four terminal sense transistor having a field plate. The method...
Gate driving device and inverter having the same
A gate driving device may include a plurality of inverter arms, respective inverter arms including a high-side switch and a low-side switch, a gate driving unit...
System and method for driving a power switch
A gate driver circuit for the power switch is disclosed. The gate driver circuit includes a resistor network coupled to the power switch. The resistor network...
Switching regulator with controllable slew rate
A driver circuit for driving a switching transistor having a control terminal responsive to a switching control signal includes a plurality of driver stages,...
Circuit having a power transistor and a drive circuit
A circuit having a power transistor and drive circuit is disclosed. One embodiment provides a drive terminal and a load path. The power transistor is integrated...