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Through silicon via including multi-material fill
An apparatus includes a substrate having at least one via disposed in the substrate, wherein the substrate includes a trench having a substantially trapezoidal...
Junction field effect transistor cell with lateral channel region
A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a...
Vertical memory device and method for making thereof
Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and...
Electrically programmable and eraseable memory device
The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the...
Semiconductor device and channel structure thereof
A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along...
Thin film, method of forming thin film, semiconductor device including
thin film, and method of manufacturing...
A thin film, a method of forming the thin film, a semiconductor device including the thin film, and a method of manufacturing the semiconductor device include...
Method for manufacturing semiconductor device including exposure of oxide
semiconductor to reducing atmosphere
A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film,...
Thin-film transistor and process for manufacture of the thin-film
A thin-film transistor includes an oxidic semiconductor channel, a metallic or oxidic gate, drain and source contacts and at least one barrier layer positioned...
Thin film transistor on fiber and manufacturing method of the same
Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second...
Integrated circuits including FINFET devices with lower contact resistance
and reduced parasitic capacitance...
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A...
Integrated circuits with fets having nanowires and methods of
manufacturing the same
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a...
Fin field effect transistor (FinFET) device structure with Ge-doped
inter-layer dielectric (ILD) structure
A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin...
Source/drain contacts for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate...
FinFET semiconductor device with isolated fins made of alternative channel
One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation...
Passivated III-V or Ge fin-shaped field effect transistor
A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and...
Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first...
Silicon-containing, tunneling field-effect transistor including III-N
Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A...
MOS transistors and fabrication methods thereof
A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second...
Methods for forming wrap around contact
Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a "finned" field-effect transistor (FinFET). An epitaxial...
Method for forming metal semiconductor alloys in contact holes and
A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing...
Power semiconductor device and method for fabricating the same
A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the...
Semiconductor device and manufacturing method thereof
A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and...
Super junction trench power MOSFET devices
In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated...
Structures of and methods of fabricating split gate MIS devices
A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly...
Transistor structure with improved unclamped inductive switching immunity
A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate...
Controlling current or mitigating electromagnetic or radiation
interference effects using multiple and...
Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using multiple different semi-conductive channel...
A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each...
Sidewall passivation for HEMT devices
Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a...
Semiconductor structure and method of forming the same
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the...
Three-dimensional memory device having a heterostructure quantum well
A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through...
Lateral bipolar transistor
A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base...
Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and...
Vertical tunnel field effect transistor
A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to...
Method for manufacturing semiconductor device
In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a...
Display array substrate and manufacturing method thereof
A manufacturing method of display array substrate is provided. The method includes depositing a first metal layer on a substrate and defining a peripheral area...
Stacked nanowires with multi-threshold voltage solution for pFETs
A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e.,...
Field effect transistor device spacers
A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack...
Stacked nanosheets by aspect ratio trapping
A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of...
Formation of high quality fin in 3D structure by way of two-step
The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a...
Methods of forming alternative channel materials on FinFET semiconductor
One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the...
Method of manufacturing semiconductor device
A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the...
Reducing variation by using combination epitaxy growth
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor...
Source/drain stressor having enhanced carrier mobility and method for
Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor...
Fabricating method of semiconductor device
A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over...
Metal oxide semiconductor having epitaxial source drain regions and a
method of manufacturing same using dummy...
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
Semiconductor device and method for manufacturing the same
A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the...
Semiconductor integrated circuit device having vertical channel and method
of manufacturing the same
A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed...
Enhancement mode III-nitride device and method for manufacturing thereof
Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing...
Semiconductor device with low-K spacers
One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a...
Semiconductor device including high-K metal gate having reduced threshold
A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer...