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Patent # Description
US-9,425,228 Image sensor with reduced optical path
Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to...
US-9,425,227 Imaging sensor using infrared-pass filter for green deduction
An imaging sensor is provided. The imaging sensor includes: a filter array used for extracting a specified color component of an incident light; and...
US-9,425,226 Imaging device
An imaging device which is capable of taking images with high quality and can be manufactured at low cost is provided. A first circuit includes a first...
US-9,425,225 Solid-state imaging device
Unit pixel cells each includes: a photoelectric conversion film; a transparent electrode; a pixel electrode; an amplification transistor; a reset transistor;...
US-9,425,224 Light detection device
A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes...
US-9,425,223 Manufacture method of TFT substrate and sturcture thereof
The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: 1, deposing a first metal layer (2) on a substrate...
US-9,425,222 Display device and method of manufacturing the same
A display device includes pixels. At least one of the pixels includes a pixel area, a first non-pixel area disposed adjacent to the pixel area and extending in...
US-9,425,221 Circuit-on-wire
A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed...
US-9,425,220 Semiconductor device
A semiconductor device having a high aperture ratio, including a capacitor with increased capacitance, and consuming low power is provided. The semiconductor...
US-9,425,219 Array substrate with data line sharing, manufacturing method thereof and display panel
An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes: a substrate; and first pixel groups and...
US-9,425,218 Pixel structure and display panel
A pixel structure disposed on a first substrate is provided. The pixel structure includes a scan line, a data line, an active component, a pixel electrode, a...
US-9,425,217 Semiconductor device
Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a...
US-9,425,216 Thin film transistor substrate having metal oxide semiconductor and manufacturing the same
The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for the fringe field type flat panel displays and a method...
US-9,425,215 Wireless processor, wireless memory, information system, and semiconductor device
The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is...
US-9,425,214 Thin film transistor substrate, method of manufacturing the same, and organic light emitting diode display...
A thin film transistor substrate includes: a polymer substrate, an oxide transparent electrode layer (TCO) formed on the polymer substrate, a barrier layer...
US-9,425,213 Stacked short and long channel FinFETs
An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an...
US-9,425,212 Isolated and bulk semiconductor devices formed on a same bulk substrate
Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure...
US-9,425,211 Semiconductor memory device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a...
US-9,425,210 Double-source semiconductor device
A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located...
US-9,425,209 Multilayer 3-D structure with mirror image landing regions
An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory...
US-9,425,208 Vertical memory devices
A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure...
US-9,425,207 Memory device with different memory film diameters in the same laminate level
According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second...
US-9,425,206 Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology
The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor...
US-9,425,205 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and a charge storage film. The stacked body includes a...
US-9,425,204 Non-volatile memory for high rewrite cycles application
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read...
US-9,425,203 Non-volatile memory cell in semiconductor device
A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a...
US-9,425,202 Split page 3D memory array
A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the...
US-9,425,201 Cell layout for SRAM FinFET transistors
An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU...
US-9,425,200 Semiconductor device including air gaps and method for fabricating the same
Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The...
US-9,425,199 Field effect transistor and method for manufacturing semiconductor device
A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode...
US-9,425,198 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first...
US-9,425,197 Semiconductor device and manufacturing method for the same
A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate...
US-9,425,196 Multiple threshold voltage FinFETs
A method of forming a plurality of fins having different threshold voltages from a single semiconductor layer without channel doping. The method may include;...
US-9,425,195 Static discharge system
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge...
US-9,425,194 Transistor devices with high-k insulation layers
An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first...
US-9,425,193 Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material
A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of...
US-9,425,192 Integrated circuit decoupling capacitors
Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit...
US-9,425,191 Memory device and manufacturing method of the same
A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a...
US-9,425,190 Techniques for providing a direct injection semiconductor memory device
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as...
US-9,425,189 Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for...
The present disclosure provides a semiconductor device including an SOI substrate comprising an active semiconductor layer disposed on a buried insulating...
US-9,425,188 Active ESD protection circuit with blocking diode
An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a...
US-9,425,187 Apparatus and methods for modulating current / voltage response using multiple semi-conductive channel regions...
Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated...
US-9,425,186 Electrostatic discharge protection circuit
The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The...
US-9,425,185 Self-healing electrostatic discharge power clamp
Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from...
US-9,425,184 Electrostatic discharge devices and methods of manufacture
Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure...
US-9,425,183 Active guard ring structure to improve latch-up immunity
An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active...
US-9,425,182 Low noise and high performance LSI device
In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering...
US-9,425,181 Method of hybrid packaging a lead frame based multi-chip semiconductor device with multiple interconnecting...
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting...
US-9,425,180 Treating copper surfaces for packaging
A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die...
US-9,425,179 Chip packages and methods of manufacture thereof
Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support...
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