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Patent # Description
US-9,425,178 RDL-first packaging process
A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through...
US-9,425,177 Method of manufacturing semiconductor device including grinding semiconductor wafer
A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of...
US-9,425,176 Cascode transistor device and manufacturing method thereof
A semiconductor device comprises a substrate, a patterned conductive layer, a first transistor structure and a second transistor structure. The patterned...
US-9,425,175 Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods
Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical...
US-9,425,174 Integrated circuit package with solderless interconnection structure
An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front...
US-9,425,173 Display device using semiconductor light emitting device
A display device according to an embodiment of the present disclosure may include a lower substrate disposed with a line electrode at an upper portion thereof,...
US-9,425,172 Light emitter array
Lamps, luminaries or solid state lighting components are disclosed having multiple discrete light sources whose light combines to provide the desired emission...
US-9,425,171 Removable substrate for controlling warpage of an integrated circuit package
One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the...
US-9,425,170 Stacked chips electrically connected by a plurality of juncture portions
An inventive semiconductor device includes: a first semiconductor chip; a second semiconductor chip having a front surface opposed to a front surface of the...
US-9,425,169 Flexible stack packages having wing portions
A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the...
US-9,425,168 Stud bump and package structure thereof and method of manufacturing the same
A stud bump structure, a package structure thereof and method of manufacturing the package structure are provided. The stud bump structure include a first chip;...
US-9,425,167 Stackable microelectronic package structures
A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon....
US-9,425,166 GOA layout method, array substrate and display device
A GOA layout method, an array substrate and a display device are provided. The array substrate includes a plurality of GOA unit groups, each of which includes...
US-9,425,165 Method of manufacturing semiconductor device
A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for...
US-9,425,164 Low alpha tin
A non alpha controlled Tin including Tin and a trace amount of Polonium may be converted to a low alpha emission Tin by concentrating and removing at least some...
US-9,425,163 Systems and methods for determining and adjusting a level of parallelism related to bonding of semiconductor...
A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure configured to support a substrate; a bond head...
US-9,425,162 Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same
A bond head for a thermocompression bonder is provided. The bond head includes a tool configured to hold a workpiece to be bonded, a heater configured to heat...
US-9,425,161 Semiconductor device with mechanical lock features between a semiconductor die and a substrate
An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with...
US-9,425,160 Wafer-level package device with solder bump reinforcement
Wafer-level package (semiconductor) devices are described that have a reinforcement layer formed on an adhesion layer and/or a semiconductor substrate and...
US-9,425,159 Wiring board and method for manufacturing the same
A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to...
US-9,425,158 Rigid-flex module and manufacturing method
Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane (20) and a sacrificial-material piece (16) are attached to an...
US-9,425,157 Substrate and package structure
According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the...
US-9,425,156 Semiconductor packages having semiconductor chips disposed in opening in shielding core plate
A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate,...
US-9,425,155 Wafer bonding process and structure
A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate....
US-9,425,154 Noise decoupling structure with through-substrate vias
A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate...
US-9,425,153 Semiconductor devices comprising getter layers and methods of making and using the same
Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or...
US-9,425,152 Method for fabricating EMI shielding package structure
An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first...
US-9,425,151 Compliant electrostatic transfer head with spring support layer
A compliant electrostatic transfer head and method of forming a compliant electrostatic transfer head are described. In an embodiment, a compliant electrostatic...
US-9,425,150 Multi-via interconnect structure and method of manufacture
An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via...
US-9,425,149 Integrated circuit package routing with reduced crosstalk
An integrated circuit package substrate may include a core layer and dielectric layers formed on top and bottom surfaces of the core layer. Routing traces such...
US-9,425,148 Semiconductor devices having contacts with intervening spacers and method for fabricating the same
Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the...
US-9,425,147 Semiconductor device
A semiconductor device includes an interlayer insulating film; a wiring formed on the interlayer insulating film so as to protrude there from and made of a...
US-9,425,146 Semiconductor structure and method for making same
One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece;...
US-9,425,145 Oversized contacts and vias in layout defined by linearly constrained topology
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second...
US-9,425,144 Metal fuse structure for improved programming capability
Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an...
US-9,425,143 Integrated device package comprising an electromagnetic (EM) passive device in an encapsulation layer, and an...
Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die...
US-9,425,142 Semiconductor device and manufacturing method of the same
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first...
US-9,425,141 Integrated circuit with elongated coupling
An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width....
US-9,425,140 Capacitors in integrated circuits and methods of fabrication thereof
In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first...
US-9,425,139 Dual row quad flat no-lead semiconductor package
Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer...
US-9,425,138 Semiconductor device having through-electrode
A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the...
US-9,425,137 Wiring board
A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first,...
US-9,425,136 Conical-shaped or tier-shaped pillar connections
A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape....
US-9,425,135 Electrode body, wiring substrate, and semiconductor device
An electrode body is provided as an electrode body capable of appropriately reducing a load when silicon wafer direct bonding is performed. The electrode body 1...
US-9,425,134 Chip package
A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or...
US-9,425,133 Integrated circuits and methods of forming conductive lines and conductive pads therefor
An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor...
US-9,425,132 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor...
US-9,425,131 Package structure
A package structure includes an insulation layer, a first conductive layer, a second conductive layer, at least one electronic component, and at least one...
US-9,425,130 Package with multiple I/O side-solderable terminals
Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending...
US-9,425,129 Methods for fabricating conductive vias of circuit structures
Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes...
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