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3-D package having plurality of substrates
A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first...
Method for forming an air gap around a through-silicon via
Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first...
Dummy structure for chip-on-wafer-on-substrate
Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of...
Silicon-glass hybrid interposer circuitry
An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon...
Compliant pin fin heat sink and methods
A heat sink includes a plurality of layers being disposed substantially parallel with a surface of a heat source. The layers include a plurality of pin portions...
Electronic device having heat conducting member
An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally...
Electronic component package and method for manufacturing the same
A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded...
Integrated fan-out structure with guiding trenches in buffer layer
A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding...
Semiconductor device and production method therefor
A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a...
Package structure and fabrication method thereof
A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts;...
Electronic component having a corrosion-protected bonding connection and
method for producing the component
The invention relates to an electronic component (1) having a corrosion-protected bonding connection and a method for producing said component. For this purpose...
Substrate design with balanced metal and solder resist density
A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer...
Integrated circuit package and a method for manufacturing an integrated
An integrated circuit package includes a package module including one or more circuit interconnections formed in a carrier, wherein at least one top-side...
Glass frit wafer bond protective structure
A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate...
Flip chip packages
A flip chip package includes a substrate, a silicon die supported on and electrically connected with the substrate, and a lid attached with the substrate and...
Package for high frequency circuits
The present invention relates to integrated circuit packaging and methods of manufacturing these. In particular, but not exclusively the present invention...
Calibration kits for RF passive devices
A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric...
A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom...
Yield enhancing vertical redundancy method for 3D wafer level packaged
(WLP) integrated circuit systems
A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been...
Planarization method, method for polishing wafer, and CMP system
A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer...
Method to prevent lateral epitaxial growth in semiconductor devices
A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of...
Memory device and method for manufacturing the same
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as...
Methods of performing fin cut etch processes for taper FinFET
semiconductor devices and the resulting devices
A method includes forming a plurality of fins above a substrate. At least one dielectric material is formed above and between the plurality of fins. A mask...
Semiconductor device including self-aligned gate structure and improved
gate spacer topography
A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the...
Complementary metal oxide semiconductor device and method of manufacturing
Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a...
Methods of using a metal protection layer to form replacement gate
structures for semiconductor devices
A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second...
FinFETs with different fin heights
An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device...
FinFET fabrication method using buffer layers between channel and
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the...
Methods of facilitating fabricating transistors
Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region...
Epitaxial channel with a counter-halo implant to improve analog gain
Some embodiments of the present disclosure relate to an implant that improves long-channel transistor performance with little to no impact on short-channel...
Radio-frequency device package and method for fabricating the same
A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate...
Cut first alternative for 2D self-aligned via
A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided....
Air gap between tungsten metal lines for interconnects with reduced RC
Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer...
Distributed metal routing
A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The...
Mechanisms for forming semiconductor device structure with feature opening
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a...
Copper wiring forming method, film forming system, and storage medium
A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate,...
Methods for producing interconnects in semiconductor devices
A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to...
Method for forming semiconductor structure
One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first...
Method of electrodepositing gold on a copper seed layer to form a gold
An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is...
Conductive element structure and method
Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating...
Manufacturing method of semiconductor device
A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the...
Method for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate. The method...
Method of controlling contact hole profile for metal fill-in
A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner...
Structures, devices and methods for memory devices
Structures, devices and methods are provided for fabricating memory devices. A structure includes: a first conductive line disposed in a first conductive layer;...
Mechanisms for forming protection layer on back side of wafer
Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device...
Handle substrate, composite substrate for semiconductor, and semiconductor
circuit board and method for...
It is provided a handle substrate of a composite substrate for a semiconductor. The handle substrate is composed of a translucent polycrystalline alumina. A...
Method of implantation for fragilization of substrates
The disclosure relates to a method for implantation of atomic or ionic species into a batch of substrates made of semiconductor material, in which: each...
Non-volatile memory device employing semiconductor nanoparticles
Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the...
Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method...
Inhibitor plasma mediated atomic layer deposition for seamless feature
Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber...