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Patent # Description
US-9,425,077 Semiconductor apparatus with transportable edge ring for substrate transport
An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with...
US-9,425,076 Substrate transfer robot end effector
Embodiments of apparatus for supporting a substrate are disclosed herein. In some embodiments, an apparatus for supporting a substrate includes a support...
US-9,425,075 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a...
US-9,425,074 Heat treatment apparatus
A heat treatment apparatus performs a heat treatment on a plurality of target objects held by a holding unit while allowing an inert gas to flow upwardly in a...
US-9,425,073 Depression filling method and processing apparatus
A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor...
US-9,425,072 Mask pattern for hole patterning and method for fabricating semiconductor device using the same
A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming...
US-9,425,071 Film forming method
A film forming method for obtaining a thin film by laminating molecular layers of oxide on a surface of a substrate in a vacuum atmosphere includes performing a...
US-9,425,070 Semiconductor device and a method of manufacturing the same
Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip...
US-9,425,069 Electronic modules
Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.
US-9,425,068 Semiconductor device, related manufacturing method, and related electronic device
A method for manufacturing semiconductor device may include the following steps: performing an etching process to remove a sacrificial layer from a first...
US-9,425,067 Method for forming package systems having interposers
A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a...
US-9,425,066 Circuit substrate
A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first...
US-9,425,065 Semiconductor device and method of manufacture thereof
A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring...
US-9,425,064 Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages
Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to...
US-9,425,063 Method of reducing an impurity concentration in a semiconductor body, method of manufacturing a semiconductor...
A method of reducing an impurity concentration in a semiconductor body includes irradiating the semiconductor body with particles through a first side of the...
US-9,425,062 Method for improving CD micro-loading in photomask plasma etching
Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask...
US-9,425,061 Buffer cap layer to improve MIM structure performance
The present disclosure relates to method of forming a MIM (metal-insulator-metal) structure having a buffer cap layer that reduces stress induced by an...
US-9,425,060 Method for fabricating multiple layers of ultra narrow silicon wires
A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and...
US-9,425,059 Methods of forming a pattern and methods of manufacturing a semiconductor device using the same
A method of forming a pattern includes forming an underlayer on an etching target layer by a chemical vapor deposition (CVD) process, the underlayer including a...
US-9,425,058 Simplified litho-etch-litho-etch process
Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several...
US-9,425,057 Method and apparatus for manufacturing three-dimensional-structure memory device
A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly...
US-9,425,056 Method for producing silicon wafer
The present invention provides a method for producing a silicon wafer including a step of, after growing the oxide film on one surface of a raw material silicon...
US-9,425,055 Split gate memory cell with a layer of nanocrystals with improved erase performance
A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first...
US-9,425,054 Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes: preparing a substrate; performing a pre-treatment including a first hydrogen annealing on a surface of...
US-9,425,053 Block mask litho on high aspect ratio topography with minimal semiconductor material damage
A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The...
US-9,425,052 Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures
Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to...
US-9,425,051 Method for producing a silicon-germanium film with variable germanium content
The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A...
US-9,425,050 System and method for providing an electron blocking layer with doping control
Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included...
US-9,425,049 Cut first self-aligned litho-etch patterning
The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a...
US-9,425,048 Mechanisms for semiconductor device structure
Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure...
US-9,425,047 Self-aligned process using variable-fluidity material
A method of forming a wide line includes forming a portion of variable-fluidity material between opposing inner walls of a pair of adjacent line portions, the...
US-9,425,046 Method for surface roughness reduction after silicon germanium thin film deposition
Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that...
US-9,425,045 Semiconductor device including oxide semiconductor and manufacturing method thereof
It is an object to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. An oxide...
US-9,425,044 Composite spacer for silicon nanocrystal memory storage
Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed...
US-9,425,043 High mobility power metal-oxide semiconductor field-effect transistors
High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is...
US-9,425,042 Hybrid silicon germanium substrate for device fabrication
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first buffer layer, a...
US-9,425,041 Isotropic atomic layer etch for silicon oxides using no activation
Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of NO...
US-9,425,040 Method of forming laminated film and forming apparatus thereof
A method of forming a laminated film includes forming a silicon oxide film on a plurality of target objects loaded in a reaction chamber, and forming a silicon...
US-9,425,039 Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory...
Provided is a technique of controlling a work function of a metal film. A composite metal nitride film is formed on a substrate present in a process chamber by...
US-9,425,038 Method and apparatus for forming silicon oxycarbonitride film, silicon oxycarbide film and silicon oxynitride film
A method for forming a silicon oxycarbonitride film includes supplying a gas containing a silicon precursor having an oxygen-containing group onto a process...
US-9,425,037 Silicon polishing compositions with improved PSD performance
The invention relates to a chemical-mechanical polishing composition comprising silica, one or more tetraalkylammonium salts, one or more bicarbonate salts, one...
US-9,425,036 Light source device and semiconductor manufacturing apparatus including the same
Provided are a light source device and a semiconductor manufacturing apparatus including the same. The light source device includes a light-emitting lamp. The...
US-9,425,035 Ion trap with spatially extended ion trapping region
A mass or mass to charge ratio selective ion trap is disclosed which directs ions into a small ejection region. A RF voltage acts to confine ions in a first (y)...
US-9,425,034 Quasi-planar multi-reflecting time-of-flight mass spectrometer
A multi-reflecting time-of-flight (MR-TOF) mass spectrometer, which includes two quasi-planar electrostatic ion mirrors extended along drift direction (Z) and...
US-9,425,033 Ion injection device for a time-of-flight mass spectrometer
The invention provides methods and devices to pulse ions from an RF ion storage into the flight tube of a time-of-flight mass spectrometer. The pusher cell...
US-9,425,032 Optimizing drag field voltages in a collision cell for multiple reaction monitoring (MRM) tandem mass spectrometry
A collision cell has a plurality of rod electrodes arranged in opposed pairs around an axial centerline and a plurality of drag vanes arranged in the...
US-9,425,031 Method and system for providing a modifier to a curtain gas for a differential mobility spectrometer
A system including a differential mobility spectrometer is described as is a method of operating the system including the differential mobility spectrometer....
US-9,425,030 Electrostatic suppression of ion feedback in a microchannel plate photomultiplier
A photomultiplier tube having an ion suppression electrode positioned between a photocathode and an electron multiplying device in the photomultiplier tube is...
US-9,425,029 Processing apparatus having a first shield and a second shield arranged to sandwich a substrate
A processing apparatus includes a supply source including a first supply source and a second supply source arranged to respectively face a first surface of a...
US-9,425,028 Plasma processing apparatus
A plasma processing apparatus includes an upper electrode arranged at a processing chamber and including a plurality of gas supplying zones, a branch pipe...
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