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Memory system, control system and method of predicting lifetime
A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through...
Reduced size semiconductor device and method for manufacture thereof
A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate...
The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing bit information. According to the invention it...
Non-volatile semiconductor memory device having depletion-type and
enhancement-type channel regions
A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by...
Semiconductor storage device
A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no...
Semiconductor memory device, operating method thereof, and data storage
device including the same
A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control...
Signal processing circuit and method for driving the same
An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage...
Memory cells, methods of forming memory cells, and methods of programming
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable...
Semiconductor storage device
According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory...
Ionic storage unit and driving method
There is provided a storage unit including: a storage device configured to store a resistance state, the resistance state being changeable between a first state...
Method for operating RRAM memory
Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory...
Semiconductor memory device and method for reading the same using a memory
cell array including resistive...
Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a...
Non-volatile semiconductor memory device
A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When...
Resistive memory apparatus and memory cell thereof
A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first...
High-speed readable semiconductor storage device
According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a...
A static RAM includes: a plurality of memory cells provided at intersections of bit line pairs and word lines; a write driver connected between a high potential...
Method and apparatus for screening memory cells for disturb failures
Embodiments include a method comprising: receiving a first voltage; and while testing a memory cell: modifying the first voltage to generate a second voltage...
There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be...
Static random access memory (SRAM) arrays having substantially constant
operational yields across multiple...
Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one...
Differential vector storage for dynamic random access memory
A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have...
Semiconductor device suppressing BTI deterioration
Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a...
Timing controller with delay time units for a semiconductor storage device
A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A...
Method of operating semiconductor memory device
A semiconductor memory device includes a variable resistance memory element connected between first and second conductive lines intersecting each other, and a...
Magnetic memory devices including oxide multiferroic material
A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality...
Memory apparatus and memory device
To provide a memory apparatus capable of operating at high speed with less current and inhibiting a decrease in an amplitude of a readout signal. A memory...
Memory controller and associated method for generating memory address
A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a...
Semiconductor memory device outputting status signal and operating method
An operating method of a semiconductor memory device may include receiving a command, outputting a status signal as a busy status while accessing a selected...
Area-efficient process-and-temperature-adaptive self-time scheme for
performance and power improvement
In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome...
Apparatuses and methods for providing active and inactive clock signals to
a command path circuit
Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active...
Data storage device
A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a...
Equalizer and semiconductor memory device including the same
Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay...
Method and system for fast initialization of a memory unit
Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic...
Semiconductor memory apparatus and data storage and power consumption
A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also...
Signal transfer circuit and operating method thereof
A signal transfer circuit includes a signal input unit suitable for generating an input signal corresponding to a first voltage level and a second voltage...
Systems and methods for acoustic wave enabled data storage
The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift...
Storage device to which memory device are connectable in multiple stages
A storage device includes a controller device and a memory device. The controller device transmits communication information to which route information is...
Methods and devices for temperature sensing of a memory device
Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module...
Semiconductor device and driving method thereof
A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third...
Multiple-port SRAM device
A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a...
Signal timing alignment based on a common data strobe in memory devices
configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers...
Apparatus with vapor-trapping pathway
Various aspects of the present disclosure are directed toward a disc drive apparatus including a disc drive actuator assembly, and a vapor-trapping pathway. The...
Hard disk device and temperature alarm circuit of hard disk device
A hard disk device includes a main body and a temperature alarm circuit. The temperature alarm circuit includes a temperature detecting module detecting an...
Pre-processing method for video data playback and playback interface
A pre-processing method for video data playback and a playback interface apparatus are provided, wherein a video receiver module receives a video data with...
Content shuffling system and method
A video system (10) includes a digital viewing device (22) having a display (32), a plurality of discrete video clips that are each associated with a first...
Method and apparatus for editing a video and/or audio program
The present invention provides a method and apparatus for editing an audio/video program. The method comprises the steps of acquiring the description...
System and method for semantic trick play
A semantic based trick play method and system in a media player is provided in which a semantic trick play command is received from a user while the user is...
Selective placement of progress bar
Methods and apparatus are disclosed for selecting the placement of a progress bar that is displayed on top of audiovisual content being presented on a display...
Method and apparatus for determining read-head deviation using orthogonal
A storage device includes read circuitry having a read head having a detector that outputs signals representing data from a first track and an adjacent track....
Data storage device with adaptive data capacity
A data storage device can have one or more data bits that are stored on a data storage medium and accessed with a transducing head. The data bits may be...
Two dimensional magnetic recording head separation calculator
A method for calculating an average phase offset in a two dimensional magnetic recording system includes calculating a phase offset as a difference between a...