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Patent # Description
US-9,424,225 Driver interface functions to interface client function drivers
In embodiments of driver interface functions to interface client function drivers, a set of serial communication protocol driver interfaces are exposed by a...
US-9,424,224 PCIe tunneling through SAS
Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled...
US-9,424,223 Tightly coupled multiprocessor system
The tightly coupled multiprocessor system includes a plurality of main processors. The main processors are connected via an inter-processor interface. Each of...
US-9,424,222 Apparatuses and methods for charge sharing across data buses based on respective levels of a data buses
Apparatuses and methods for charge sharing across data buses based on respective levels of the data buses are disclosed herein. An example apparatus may include...
US-9,424,221 Automated cabling process for a complex environment
A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis...
US-9,424,220 Method and apparatus for setting working mode of multi-processor system
A method for setting a working mode of a multi-processor system includes: detecting, after a current board is inserted into a slot of the backplane, whether an...
US-9,424,219 Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device...
US-9,424,218 SAS expander with non-blocking virtual phy architecture
A SAS expander includes a switch core, a number of SAS expander phys coupled to the switch core, an SMP originator coupled to the switch core and an SMP...
US-9,424,217 Methods and devices for finding settings to be used in relation to a sensor unit connected to a processing unit
A method performed in a processing unit for finding settings to be used in relation to a sensor unit connected to the processing unit is disclosed. The method...
US-9,424,216 Ascertaining configuration of a virtual adapter in a computing environment
A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The...
US-9,424,215 USB based virtualized media system
In a virtualized desktop system an interfacing module is coupled to peripheral ports of a target device. The interfacing module is connected to a network. A...
US-9,424,214 Network interface controller with direct connection to host memory
A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet...
US-9,424,213 Processing system with interspersed processors DMA-FIFO
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct...
US-9,424,212 Operating system-managed interrupt steering in multiprocessor systems
An operating system is provided in which an interrupt router dynamically steers each interrupt to one or more processors within set of processors based on...
US-9,424,211 Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller
Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller...
US-9,424,210 SDRAM memory organization and efficient access
Various structures and methods are disclosed related to efficiently accessing a memory for a particular application. An embodiment of the present invention...
US-9,424,209 Dynamic heterogeneous hashing functions in ranges of system memory addressing space
Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional...
US-9,424,208 System for controlling association of microphone and speakers
A method includes steps determining individual ones of speakers and microphones connected to a first computerized appliance by execution of a software routine,...
US-9,424,207 Information processing device, program, information processing method, and information processing system
Consistent with embodiments of this disclosure, an information processing apparatus is provided. The information processing apparatus comprises an input...
US-9,424,206 Command executing method, connector and memory storage device
A command executing method, a connector and a memory storage device are provided. The command executing method includes: receiving at least one command and at...
US-9,424,205 System and method for SATA virtualization and domain protection
A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA...
US-9,424,204 Caching method for distributed storage system, a lock server node, and a lock client node
A caching method for a distributed storage system, a lock server node, and a lock client node is disclosed. When the lock server node receives a first lock...
US-9,424,203 Storing look-up table indexes in a return stack buffer
A return stack buffers (RSB) is modified to store index values instead of addresses. When a function is called, the address following the function call is...
US-9,424,202 Database search facility
A database cache manager for controlling a composition of a plurality of cache entries in a data cache is described. Each cache entry is a result of a query...
US-9,424,201 Migrating pages of different sizes between heterogeneous processors
One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method...
US-9,424,200 Continuous run-time integrity checking for virtual memory
A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions...
US-9,424,199 Virtual input/output memory management unit within a guest virtual machine
A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device....
US-9,424,198 Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory
A processor includes at least one execution unit, a near memory, and memory management logic to manage the near memory and a far memory external to the...
US-9,424,197 Hard disk drive with optional cache memory
A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably...
US-9,424,196 Adjustment of the number of task control blocks allocated for discard scans
A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in...
US-9,424,195 Dynamic remapping of cache lines
A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A...
US-9,424,194 Probabilistic associative cache
A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but...
US-9,424,193 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
US-9,424,192 Private memory table for reduced memory coherence traffic
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor...
US-9,424,191 Scalable coherence for multi-core processors
An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based...
US-9,424,190 Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
Systems and methods are disclosed for a computer system that includes a first load/store execution unit 210a, a first Level 1 L1 data cache unit 216a coupled to...
US-9,424,189 Systems and methods for mitigating write-back caching failures
A computer-implemented method for mitigating write-back caching failures may include (1) detecting a failure that impairs at least one write-back cache that...
US-9,424,188 Non-volatile memory packaging system with caching and method of operation thereof
A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module...
US-9,424,187 Policy-based storage of portions of an object in a multi-tiered storage system
Some embodiments are directed to an object addressable storage (OAS) system that stores a plurality of objects, a method for use in an OAS system and at least...
US-9,424,186 Method and apparatus for controlling memory startup
Embodiments of the present invention disclose a method and an apparatus for controlling memory startup, and relate to the field of memory control technologies....
US-9,424,185 Method and system for garbage collection of data storage systems
A garbage collector of a storage system traverses a namespace of a file system of the storage system to identify segments that are alive in a breadth-first...
US-9,424,184 Apparatus, systems, and methods for nameless writes
An apparatus, system, and method are disclosed for implementing nameless storage operations. Storage clients can access and allocate portions of an address...
US-9,424,183 Data storage device and method for operating the same
An operating method of a data storage device includes receiving a write request, determining whether it is possible to perform a first write operation of...
US-9,424,182 Adaptive memory system for enhancing the performance of an external computing device
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a...
US-9,424,181 Address mapping for solid state devices
Technologies are generally described for systems, devices and methods relating to swapping bits in memory addresses in solid state devices. In some examples, a...
US-9,424,180 System for increasing utilization of storage media
A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing...
US-9,424,179 Systems and methods for latency based data recycling in a solid state memory system
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The...
US-9,424,178 Optimized flash memory without dedicated parity area and with reduced array size
A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is...
US-9,424,177 Clock switching method, memory controller and memory storage apparatus
A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an...
US-9,424,176 Robust sector ID scheme for tracking dead sectors to automate search and copydown
A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status...
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