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Patent # Description
US-9,431,423 Semiconductor integrated circuit
Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and...
US-9,431,422 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-9,431,421 Data line arrangement and pillar arrangement in apparatuses
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed...
US-9,431,420 Semiconductor devices including vertical cell strings that are commonly connected
A semiconductor device includes bit lines on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided...
US-9,431,419 Semiconductor memory device and method for manufacturing same
According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each...
US-9,431,418 Vertical memory devices and methods of manufacturing the same
A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of...
US-9,431,417 Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a plurality of stacks, a...
US-9,431,416 Vertical-type nonvolatile memory device and method of manufacturing the same
A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel...
US-9,431,415 Semiconductor device with vertical memory
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on...
US-9,431,414 Vertical memory devices and methods of manufacturing the same
Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective...
US-9,431,413 STI recess method to embed NVM memory in HKMG replacement gate technology
The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG...
US-9,431,412 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a first array extending in a first direction, a second array extending in the first...
US-9,431,411 Efficient process for 3D NAND memory with socketed floating gate cells
A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different...
US-9,431,410 Methods and apparatuses having memory cells including a monolithic semiconductor channel
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of...
US-9,431,409 Method of making a three-dimensional memory array with etch stop
A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially...
US-9,431,408 Methods for fabricating integrated circuits with a high-voltage MOSFET
Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon...
US-9,431,407 Method of making embedded memory device with silicon-on-insulator substrate
A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first...
US-9,431,406 Semiconductor device and method of forming the same
A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively...
US-9,431,405 Method for forming flash memory devices
A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The...
US-9,431,404 Techniques providing high-k dielectric metal gate CMOS
A semiconductor device includes a dielectric layer on a substrate, a P-type transistor having a first gate stack embedded in the dielectric layer, and an N-type...
US-9,431,403 Semiconductor device and method for manufacturing the same
A semiconductor device provided with a capacitor that includes a plurality of cylindrical or columnar storage electrodes provided periodically on a...
US-9,431,402 Semiconductor device having buried bit line and method for fabricating the same
A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the...
US-9,431,401 Memory device comprising electrically floating body transistor
A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.
US-9,431,400 Semiconductor memory device and method for manufacturing the same
A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in...
US-9,431,399 Method for forming merged contact for semiconductor device
A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a...
US-9,431,398 Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering
According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second...
US-9,431,397 Method for fabricating a multi-gate device
A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks...
US-9,431,396 Single diffusion break with improved isolation and process window and reduced cost
Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a...
US-9,431,395 Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high...
US-9,431,394 Power semiconductor package with gate and field electrode leads
A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing...
US-9,431,393 Semiconductor device
A semiconductor device includes: a first well provided in a semiconductor substrate; a second well provided in the semiconductor substrate, so as to be isolated...
US-9,431,392 Electronic circuit having adjustable transistor device
A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region...
US-9,431,391 Gallium nitride hemt device with a mosfet in series coupled to diodes for protection of high-voltage
A semiconductor device having high breakdown withstand voltage includes a first element which is a normally-on type transistor made of nitride compound...
US-9,431,390 Compact electrostatic discharge (ESD) protection structure
A multi-gate Schottky depletion-mode field effect transistor (FET), at least one diode and two resistors comprise a compact electrostatic discharge (ESD)...
US-9,431,389 ESD transistor for high voltage and ESD protection circuit thereof
An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink...
US-9,431,388 Series-connected nanowire structures
Series-connected nanowire structures and methods of manufacture are disclosed. The structure includes a plurality of vertically stacked nanowires extending...
US-9,431,387 Electrostatic discharge protection
A device comprising an electrostatic discharge protection structure, an ion sensitive field effect transistor (ISFET) having a floating gate, and a sensing...
US-9,431,386 Current sensing of emitter sense insulated-gate bipolar transistor (IGBT)
A control circuit and method are disclosed for controlling a current sense Insulated-Gate Bipolar Transistor (IGBT). In particular, the current sense IGBT...
US-9,431,385 Semiconductor component that includes a common mode filter and method of manufacturing the semiconductor component
In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode...
US-9,431,384 Programmable ESD protection circuit
An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a...
US-9,431,383 Integrated circuit, semiconductor device based on integrated circuit, and standard cell library
An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each...
US-9,431,382 Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor...
Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a...
US-9,431,381 System and method of processing cutting layout and example switching circuit
A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if...
US-9,431,380 Microelectronic assembly having a heat spreader for a plurality of die
A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure...
US-9,431,379 Signal transmission arrangement
A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.
US-9,431,378 Light-emitting diodes
A light-emitting diode includes a carrier including a metallic basic body having an outer face including a mounting face; and at least two light-emitting diode...
US-9,431,377 Light emitting device and method of fabricating the same
Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells...
US-9,431,376 Substrate for mounting multiple power transistors thereon and power semiconductor module
Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are...
US-9,431,375 High density microelectronics packaging
Example packaging of microelectronics and example methods of manufacturing the same are provided herein. The packaging can enable and/or improve the use of the...
US-9,431,374 Semiconductor package
A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different...
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