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Patent # Description
US-9,431,373 Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure,...
A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities...
US-9,431,372 Multi-chip package
A multi-chip package includes first and second semiconductor chips that are sequentially stacked, each of the first and second semiconductor chips including an...
US-9,431,371 Semiconductor package with a bridge interposer
There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active...
US-9,431,370 Compliant dielectric layer for semiconductor device
Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through...
US-9,431,369 Antenna apparatus and method
An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the...
US-9,431,368 Three dimensional device integration method and integrated device
A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a...
US-9,431,367 Method of forming a semiconductor package
A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The...
US-9,431,366 Selective area heating for 3D chip stack
A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of...
US-9,431,365 Apparatus for bonding semiconductor chips
A semiconductor chip bonding apparatus includes a bonding head to adsorptively pick up a semiconductor chip, a bonding stage supporting a substrate, the...
US-9,431,364 Multi-chip package assembly with improved bond wire separation
A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip...
US-9,431,363 Wire bonded IC components to round wire
A circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, and one or more round wire segments attached to the...
US-9,431,362 Semiconductor module
A semiconductor module includes a first semiconductor chip including a first signal line and a first ground, a mounting board or a second semiconductor chip...
US-9,431,361 Ball arrangement for integrated circuit package devices
An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in...
US-9,431,360 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate including a front side, a conductive bump disposed over the front side, and an opaque molding disposed over the...
US-9,431,359 Coaxial solder bump support structure
A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD)...
US-9,431,358 Amplifier
An amplifier includes: a first transistor that includes a first main electrode, a second main electrode, and a first control electrode, a first input signal...
US-9,431,357 Wiring board and high frequency module using same
A high frequency module wiring board includes a wiring section for high frequency transmission, and a solder resist layer formed upon the wiring section. The...
US-9,431,356 Semiconductor device and method of forming the same
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over...
US-9,431,355 Semiconductor structure and method for forming the same
Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring...
US-9,431,354 Activating reactions in integrated circuits through electrical discharge
Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated...
US-9,431,353 Method for manufacturing a digital circuit and digital circuit
A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an...
US-9,431,352 Chip with shelf life
A semiconductor structure including a recess within a silicon substrate of an integrated circuit (IC) chip, wherein the recess is located near a circuit of the...
US-9,431,351 Semiconductor package and manufacturing method of the same
The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a...
US-9,431,350 Crack-stopping structure and method for forming the same
A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal...
US-9,431,349 Rule clean layer marker
A method and apparatus for including human readable text in a semiconductor design which is both machine readable for printing on a wafer and human readable...
US-9,431,348 Semiconductor device manufacturing method and manufacturing device for marking a crystal defect
A marker which is a reference of a coordinate position defining a region of a chip that is manufactured in a semiconductor substrate is formed. A crystal defect...
US-9,431,347 Wiring board and method for manufacturing the same
A wiring board includes a first insulation layer, first conductive patterns formed on the first insulation layer and including first mounting pads positioned to...
US-9,431,346 Graphene-metal E-fuse
A structure including an M.sub.x level including a first M.sub.x metal, a second M.sub.x metal, and a third M.sub.x metal abutting and electrically connected in...
US-9,431,345 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.
US-9,431,344 Semiconductor device
A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first...
US-9,431,343 Stacked damascene structures for microelectronic devices
A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect...
US-9,431,342 Staggered via redistribution layer (RDL) for a package and a method for forming the same
An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a...
US-9,431,341 Semiconductor device having metal patterns and piezoelectric patterns
Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an...
US-9,431,340 Wiring structure for trench fuse component with methods of fabrication
The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse...
US-9,431,339 Wiring structure for trench fuse component with methods of fabrication
The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse...
US-9,431,338 Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die
A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die,...
US-9,431,337 Semiconductor device having an inner power supply plate structure
A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance...
US-9,431,336 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first...
US-9,431,335 Molding compound supported RDL for IC package
A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality...
US-9,431,334 Semiconductor device having single layer substrate and method
In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the...
US-9,431,333 Wiring substrate
A wiring substrate includes a wiring layer. Metal posts are arranged on the wiring layer. The metal posts are used to mount an electronic component. A...
US-9,431,332 Semiconductor package
A semiconductor package comprising: a semiconductor chip comprising a first surface on a first side of the semiconductor chip and a second surface on a second...
US-9,431,331 Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and...
A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film...
US-9,431,330 System and method for metal matrix mounting scheme
An integrated circuit assembly element formed via an additive manufacturing technique, such as mixing a conductive material with a memory metal to form a...
US-9,431,329 High efficiency module
A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter...
US-9,431,328 Power device and preparation method thereof
A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles...
US-9,431,327 Semiconductor device
A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame...
US-9,431,326 Semiconductor device and manufacturing method thereof
In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the...
US-9,431,325 Semiconductor packaging structure
A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a...
US-9,431,324 Semiconductor device having contact structures
A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit...
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