Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,431,323 Conductive pad on protruding through electrode
To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The...
US-9,431,322 Semiconductor device having stacked chips
According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for...
US-9,431,321 Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a...
US-9,431,320 Methods and structures to facilitate through-silicon vias
In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an...
US-9,431,319 Exposed, solderable heat spreader for integrated circuit packages
An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic...
US-9,431,318 Electronic device
In an electronic device, a one-side heat radiation element and a two-side heat radiation element are disposed on a surface of a substrate adjacent to a heat...
US-9,431,317 Power doubler amplifier module with improved solder coverage between a heat sink and a thermal pad of a circuit...
In one embodiment, an apparatus includes a printed circuit board, and a circuit package mounted to the printed circuit board. The circuit package has a thermal...
US-9,431,316 Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation
A semiconductor device has semiconductor die mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. A channel is formed in a back...
US-9,431,315 Chemical sensor package for highly pressured environment
A package for a chemical sensor including an encapsulation and a pressure balancing structure is disclosed. The encapsulation encapsulates a chemical sensor and...
US-9,431,314 Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device
A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux...
US-9,431,313 Integrated circuit carrier coating
A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a...
US-9,431,312 Wafer-scale package including power source
A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a...
US-9,431,311 Semiconductor package with elastic coupler and related methods
A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of...
US-9,431,310 Simulation method, simulation program, process control system, simulator, process design method, and mask...
A simulation method includes acquiring processing conditions for performing an etching process using plasma on a surface of a wafer covered by a mask having a...
US-9,431,309 Method for wafer level reliability
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 .ANG. on a...
US-9,431,308 Critical size compensating method of deep groove etching process
A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking...
US-9,431,307 Semiconductor wafer evaluation method, semiconductor wafer evaluation device, and probe for semiconductor...
Provided is a semiconductor wafer evaluation method of performing an evaluation of electrical characteristics of a semiconductor wafer by bringing mercury into...
US-9,431,306 Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of...
A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on...
US-9,431,305 Vertical transistor fabrication and devices
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first...
US-9,431,304 Method and structure for metal gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed...
US-9,431,303 Contact liners for integrated circuits and fabrication methods thereof
Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a...
US-9,431,302 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,431,301 Nanowire field effect transistor (FET) and method for fabricating the same
A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a...
US-9,431,300 MOL architecture enabling ultra-regular cross couple
A method of forming an ultra-regular layout with unidirectional M1 metal line and the resulting device are disclosed. Embodiments include forming first and...
US-9,431,299 Package substrate dividing method
A package substrate is divided into a plurality of device packages. An adhesive tape is attached to a back side of the substrate by cutting the substrate along...
US-9,431,298 Integrated circuit chip customization using backside access
An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit...
US-9,431,297 Method of forming an interconnect structure for a semiconductor device
Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer...
US-9,431,296 Structure and method to form liner silicide with improved contact resistance and reliablity
A contact structure with improved contact resistance and reliability is provided by forming an inner spacer between a contact liner and dielectric layers...
US-9,431,295 Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of...
An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at...
US-9,431,294 Methods of producing integrated circuits with an air gap
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a...
US-9,431,293 Selective local metal cap layer formation for improved electromigration behavior
A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and...
US-9,431,292 Alternate dual damascene method for forming interconnects
After forming at least one opening in a material stack comprising a sacrificial metal template layer overlying a first dielectric material layer, a sacrificial...
US-9,431,291 Method of making openings in a semiconductor device with reduced residue by transferring layers
According to an embodiment, a method for manufacturing a semiconductor device includes transferring a continuous second layer, forming a third layer, and...
US-9,431,290 Semiconductor device and manufacturing method therefor
A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform...
US-9,431,289 Method and structure to reduce FET threshold voltage shift due to oxygen diffusion
Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen...
US-9,431,288 System and method for test key characterizing wafer processing state
Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow...
US-9,431,287 Chemical mechanical planarization process and structures
A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the...
US-9,431,286 Deep trench with self-aligned sinker
A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench...
US-9,431,285 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first...
US-9,431,284 Device for machining a substrate and a method for this purpose
In a device for machining, in particular etching and/or developing, substrates, in particular wafers, in particular etching and/or developing, having a...
US-9,431,283 Direct electrostatic assembly with capacitively coupled electrodes
A system and method manipulate micro objects. A field generator is configured to generate a force field varying in both space and time to manipulate the micro...
US-9,431,282 Wafer inversion mechanism
A BOLTS compatible module includes a support mechanism for gripping a wafer. The support mechanism is coupled to a rotary mechanism for rotating the support...
US-9,431,281 Temperature control method for substrate heat treatment apparatus, semiconductor device manufacturing method,...
The present invention provides a temperature control method for a substrate heat treatment apparatus that achieves high throughput while securing stability in...
US-9,431,280 Self-lockable opening and closing mechanism for vacuum cabin door
A self-lockable opening and closing mechanism includes a frame, a vacuum cabin door, a driving cylinder mounted in the frame, and a linkage mechanism formed of...
US-9,431,279 Heater block and a substrate treatment apparatus
The present invention relates to a heater block and a substrate treatment apparatus, and more particularly to a heater block to perform heat treatment on a...
US-9,431,278 Backside rapid thermal processing of patterned wafers
Apparatus and methods of thermally treating a wafer or other substrate, such as rapid thermal processing (RTP) apparatus and methods are disclosed. An array of...
US-9,431,277 Substrate treatment method and substrate treatment apparatus
A substrate treatment method for treating a substrate including a first silicon nitride film provided on a front surface thereof and a silicon oxide film...
US-9,431,276 Substrate processing apparatus and substrate processing method
A rinsing liquid (DIW) is discharged from a rinsing liquid discharge port formed in a blocking member to perform rinsing processing to a substrate surface while...
US-9,431,275 Wire bond through-via structure and method
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer...
US-9,431,274 Method for reducing underfill filler settling in integrated circuit packages
Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.