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Patent # Description
US-9,431,273 Method for manufacturing a resin-encapsulated semiconductor device
A resin-encapsulated semiconductor device includes a semiconductor element mounted on a die pad portion, a plurality of lead portions arranged so that leading...
US-9,431,272 Printed circuit board including through region and semiconductor package formed by using the same
Provided is a printed circuit board (PCB). The PCB includes a board body that includes a first surface and a second surface opposite the first surface, a...
US-9,431,271 Heat dissipating device
A heat dissipating device includes a base and a plurality of heat dissipating fins. The base includes a substrate and a box, wherein the substrate and the box...
US-9,431,270 Method for producing semiconductor device
A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep...
US-9,431,269 Dual chamber plasma etcher with ion accelerator
The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus...
US-9,431,268 Isotropic atomic layer etch for silicon and germanium oxides
Methods for controlled isotropic etching of layers of silicon oxide and germanium oxide with atomic scale fidelity are provided. The methods make use of a...
US-9,431,267 Semiconductor device processing tools and methods for patterning substrates
In some embodiments, an electronic device processing system is provided that includes a processing tool having a first subsystem configured to carry out a first...
US-9,431,266 Double patterning method
Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography...
US-9,431,265 Fin cut for tight fin pitch by two different sit hard mask materials on fin
Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of...
US-9,431,264 Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask...
US-9,431,263 Plasma processing method and apparatus
A plasma processing method to a substrate includes a first step of mounting a transfer carrier holding the substrate on a stage which is cooled and provided...
US-9,431,262 Method for polishing work and work polishing apparatus
The method of the present invention is capable of polishing a high hardness work at high polishing efficiency. The method comprises the steps of: pressing a...
US-9,431,261 Removal of defects by in-situ etching during chemical-mechanical polishing processing
Technologies for a process used to reduce the height of a raised profile of a device. One or more raised profiles on one or more layers of a device are removed...
US-9,431,260 Semiconductor device and manufacturing method of the same
There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing...
US-9,431,258 Method for photodepositing a particle on a graphene-semiconductor hybrid panel and a semiconductor structure
A method for photodepositing a particle on a graphene-semiconductor hybrid panel is disclosed. The method for photodepositing the particle on the...
US-9,431,257 Salicided structure to integrate a flash memory device with a high .kappa., metal gate logic device
An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the...
US-9,431,256 Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein...
US-9,431,255 Method for etching high-k metal gate stack
A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a...
US-9,431,254 One-time programmable memory and method for making the same
A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and...
US-9,431,253 Fabrication flow based on metal gate process for making low cost flash memory
An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions...
US-9,431,252 Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack...
US-9,431,251 Semiconductor device having a double deep well and method of manufacturing same
A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant...
US-9,431,250 Deep well implant using blocking mask
Various methods include: forming an opening in a resist layer to expose a portion of an underlying blocking layer; performing an etch on the exposed portion of...
US-9,431,249 Edge termination for super junction MOSFET devices
In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region...
US-9,431,248 High tilt angle plus twist drain extension implant for CHC lifetime improvement
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one...
US-9,431,247 Method for ion implantation
A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel...
US-9,431,246 Semiconductor device with low contact resistance SIC region
According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC....
US-9,431,245 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is...
US-9,431,244 Laser annealing technique for metal oxide TFT
This disclosure provides methods and apparatuses for annealing an oxide semiconductor in a thin film transistor (TFT). In one aspect, the method includes...
US-9,431,243 Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for...
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading...
US-9,431,242 PBNZT ferroelectric film, sol-gel solution, film forming method and method for producing ferroelectric film
To provide a PBNZT ferroelectric film capable of preventing sufficiently oxygen ion deficiency. The PBNZT ferroelectric film according to an embodiment of the...
US-9,431,241 Method for manufacturing a silicon nitride thin film using plasma-enhanced chemical vapor deposition
A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below...
US-9,431,240 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor is provided. The method includes forming a thin film including a predetermined element and a borazine ring skeleton is...
US-9,431,239 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate;...
US-9,431,238 Reactive curing process for semiconductor substrates
In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen...
US-9,431,237 Post treatment methods for oxide layers on semiconductor devices
Methods and apparatus for post treating an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, the oxide layer is formed by...
US-9,431,236 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes forming a thin film containing a specific element, oxygen, carbon, and nitrogen by performing a cycle...
US-9,431,235 Multilayer dielectric structures with graded composition for nano-scale semiconductor devices
Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films,...
US-9,431,234 Curable polymeric materials and their use for fabricating electronic devices
Disclosed are curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In...
US-9,431,233 Plasma lighting system with a metallic material in the bulb
A plasma lighting system includes a magnetron configured to generate microwaves, and a bulb in which a dose for generation of light using the microwaves and at...
US-9,431,232 Short arc discharge lamp
A cathode for a discharge lamp in which an electron emitting section containing an easily electron emitting material at its end is provided that has simplified...
US-9,431,231 Lamp with graded absorption coating
The invention describes a lamp (1A, 1B, 1C, 1D) comprising a glass envelope (10) enclosing a light generating means (11), and an axially and/or...
US-9,431,230 Method of extracting ions with a low M/Z ratio from an ion trap
In a mass spectrometer, a method for trapping ions includes providing at least first and second multipole rod sets positioned in tandem, introducing a plurality...
US-9,431,229 Sputter neutral particle mass spectrometry apparatus with optical element
A sputter neutral particle mass spectrometry apparatus includes a sample table holding a sample which is a mass spectrometry target, an ion beam irradiation...
US-9,431,228 Ion lens for reducing contaminant effects in an ion guide of a mass spectrometer
An ion lens for reducing contaminant effects in an ion guide of a mass spectrometer is provided. The ion lens comprises a structural member comprising an...
US-9,431,227 Sample transferring apparatus for mass cytometry
In a mass cytometer or mass spectrometer, a sample of elemental tagged particles is transferred from a dispersion to a gas flow through a carrier aerosol spray...
US-9,431,226 High-voltage power unit and mass spectrometer using the power unit
An output terminal of a positive voltage generating circuit and an output terminal of a negative voltage generating circuit are connected in series, and an...
US-9,431,224 Chromatograph mass spectrometer
When performing an automatic MS.sup.2 analysis on a specimen containing components that include elements whose abundance ratio of stable isotopes is close, to...
US-9,431,223 Imaging mass spectrometry method and device
A method of performing imaging mass spectrometry of a sample. The method comprises performing a first mass analysis of the sample using a first mass analyzer...
US-9,431,222 Device and method for measuring an energy particle beam
The present invention relates to a dosimetry device for an energy particle beam from a source and including at least two ionization chambers, each of which...
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